JP2723703B2 - Arithmetic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit, and more particularly to an arithmetic circuit for calculating and outputting the outputs of a peak hold circuit and a bottom hold circuit.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional arithmetic circuit of this type corresponds to signal input sources 37 and 38, a high potential power supply terminal 57, a low potential power supply terminal 56 and an output terminal 58. And an amplifier 21, a diode 22, a constant current source 2
Hold circuit 25 including capacitor 3 and capacitor 24
And a bottom hold circuit 30 including an amplifier 26, a diode 27, a constant current source 28, and a capacitor 29, and an operational amplifier circuit 36 including resistors 31 to 34 and an amplifier 35. FIGS. 4A and 4B are diagrams showing input / output signal waveforms in the peak hold circuit 25 and the bottom hold circuit 30, respectively.

In FIG. 3, a signal input source 3 is connected to a positive-phase input terminal of an amplifier 21 included in a peak hold circuit 25.
7, a signal 105 having 0 V as a reference voltage is input. In the initial state, the potential of the potential V ₊ and the negative phase input terminal of the positive-phase input terminal of the amplifier 21 V _- are both a 0V. Input signal 1 input to the positive-phase input terminal
Until the level of 05 reaches the peak voltage on the positive side,
Since a forward bias voltage is applied to the diode 22 and the amplifier 21 operates as a full feedback amplifier, the potential V ₋ of the negative-phase input terminal is equal to the potential V ₊ of the positive-phase input terminal. It operates to be at a potential. Therefore,
The capacitor 24 is charged by the constant current I ₅ of the constant current source 23, and the input signal 1
A signal 107 having the same level as that of the signal 05 is output.

[0004] Then, when the potential V ₊ of the input signal 105 with respect to the positive phase input terminal of the amplifier 21 is lower than the peak value, the potential of the negative-phase input terminal V _- also tries to drop by following, V ₊ <V _- And the reverse bias voltage is applied to the diode 22, so that the diode 2
2, the discharge current from the capacitor 24 is cut off, and the potential of the signal 107 is held by the capacitor 24 at the same potential level corresponding to the peak voltage (V _imax ) of the input signal 105. However, since the constant current source 23 (current value: I ₅ ) is connected in parallel to the capacitor 24, the potential of the signal 107 held by the capacitor 24 (capacitance value: C ₂₄ ) is equal to the time T _o to time T ₁
During the elapse of the period from the peak voltage V _imax to V _hold
However, the time constant T _dis in this case is given by the following equation.

T _dis = [(V _imax −V _hold ) × C ₂₄ ] / I ₅ (1) Next, in the bottom hold circuit 30, the amplifier 26
Is input from the signal input source 38 with an input signal 106 having a reference voltage of 0 V and a phase inversion of the input signal 105 by 180 degrees. The operation of the bottom hold circuit 30 in this case is basically the same as the operation of the peak hold circuit 25 described above, but since the connection direction of the diode 27 is opposite to the connection direction of the diode 22, As the potential of the signal 108 output from the capacitor 30, the capacitor 29 has the potential shown in FIG.
At time To, as shown in FIG.
6, the bottom voltage V _imin is held. However, the bottom voltage V _imin held in the capacitor 29 is
A constant current source 2 for the capacitor 29 (capacity value: C ₂₉ )
8 (current value: I ₆ ) are connected in parallel, and at time T ₁ , the voltage _rises from the bottom voltage V _imin to V _hold . In this case, the time constant T _dis is given by the following equation. .

T _dis = [(V _hold −V _imin ) × C ₂₉ ] / I ₆ (2) The potentials of the signals 107 and 108 are calculated by the operational amplifier 3
6, the operational amplifier 36 functions as a subtractor. If the voltages of the signals 107 and 108 are V ₁₀₇ and V ₁₀₈ respectively, the voltage output from the output terminal 58 of the operational amplifier 36 is V _out is given by the following equation.

V _out = V ₁₀₈ −V ₁₀₇ ... ...... (3)

In [0008] conventional operational circuit described above, the peak hold circuit 25, amplifier 21, V _+> V _- In under input conditions of, V ₊
= V _- and operates so, V ₊ <V _- In input conditions, in the voltage applied to the diode 22 becomes a reverse bias voltage, the feedback is not applied to the amplifier 21. Figure 4 as the state at time t _o of (a), the input state is V _+> V _- next, V ₊ and V _- when the potential difference V _d is generated between the open gain of the amplifier 21 A as _v21, the voltage V ₁₀₇ of the signal 107 outputted from the peak hold circuit 25 is given by the following equation.

V ₁₀₇ = V _d × A _v21 (4) _{Assuming that} the open gain of a normal operational amplifier is about 60 dB, the potential difference V _d is about 1 mV. The above voltage V
_{In 107} , it changes by 1v. Thus, voltage V ₁₀₇ will rise sharply, as shown at time t ₁ . Then, in the time t ₁ and later,
Since V ₊ <V ₋ , the amplifier 21 operates to increase the output voltage.
Since it is applied a reverse bias voltage to the voltage value held in the voltage V _107, it is gradually discharged by a time constant represented by the above formula (1), at time t ₂ later, by the same operation is performed repeatedly, the signal 107 outputted from the peak hold circuit 25, the ringing of V ₁ is generated as shown in Figure 4 (a).
Similarly, in the bottom hold circuit 30, FIG.
As shown in (b), it is performed the same operation as of the peak hold circuit 25 at time t _o ~t _2, by which the operation is repeated, the bottom hold circuit 3
The signal 108 outputted from 0, ringing V ₂ occurs.

Therefore, the output terminal 58 of the operational amplifier circuit 36
Voltage V _out output from the, in the time T _o in Fig. _{4 (a), V 107 =} V imax + V 1 , and the FIG. 4
In (b) at time T _o, V ₁₀₇ = -V _imin
Since the -V _2, when put the V _imax = V _imin to equality and an absolute value of the absolute value and the V _imin of V _imax, given by the following equation.

V ₁₀₇ = − (V _imin + V ₂ ) − (V _imax + V ₁ ) = − _{2V imax} − (V ₁ + V ₂ ) (5) That is, the output of the operational amplifier circuit 36 The voltage V _out has a drawback that (V ₁ + V ₂ ) shown in the above equation occurs as an offset voltage.

[0011]

An arithmetic circuit according to the present invention has an emitter connected to a power supply on the high potential side via a first constant current source, a base connected to a first input signal source, and a collector connected to the collector. Are connected to a low-potential-side power supply, a collector is connected to the high-potential-side power supply, a base is connected to the emitter of the first PNP transistor, and an emitter is connected to the second PNP transistor. A peak hold circuit including a first NPN transistor connected to a low-potential power supply through a parallel circuit of a constant current source and a first capacitor; a collector connected to a high-potential power supply; Is connected to the second input signal source, the second NPN transistor whose emitter is connected to the lower potential side power supply via the third constant current source, and the emitter is the fourth constant current source and the fourth constant current source. Parallel with 2 capacitors Through the road is connected to the power supply on the high potential side, the base of the second NPN transistor emitter
Is connected to an arithmetic circuit for performing a second PNP transistor having a collector Ru is connected to the power supply on the low potential side, a bottom hold circuit including a calculation by inputting the output of the peak hold circuit and the bottom hold circuit And the bases of the first and second PNP transistors and the first and second NPN transistors.
The reverse saturation current value between the emitters is set to the same current value,
Further, the current values of the first, second, third and fourth constant current sources are set to the same value.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, in the present embodiment, the signal input sources 19 and 20 and the high potential power supply terminals 51 and 53,
Corresponding to the low-potential power supply terminals 52 and 54 and the output terminal 55, a peak hold circuit 6 including a PNP transistor 1 and an NPN transistor 2, constant current sources 3 and 4, and a capacitor 5, and NPN transistors 7 and P
A bottom hold circuit 12 including an NP transistor 8, constant current sources 9 and 10, and a capacitor 11;
3 to 16 and an operational amplifier circuit 18 including an amplifier 17. FIGS. 2A and 2B
3 is a diagram showing input / output signal waveforms in the peak hold circuit 6 and the bottom hold circuit 12, respectively.
In the present embodiment, the maximum voltage V _imax and the minimum voltage V _imin of the input signal are equal in absolute value.

In FIG. 1, a signal 101 having a reference voltage of 0 V is applied from a signal input source 19 to the base of the PNP transistor 1 included in the peak hold circuit 6 (FIG. 2).
(A) the voltage V ₁₀₁ of the reference) is input. In the initial state, the voltage V ₁₀₁ of the signal 101 input to the base of the PNP transistor 1 has a 0V. Looking at the elapsed time from the input of the signal 101 to the time T _o , the following operation progresses.

[0015] The maximum voltage of the signal 101 at time T _o V _imax, when the voltage between the base-emitter voltage of V _BE1, NPN transistor 2 between the base and the emitter of the PNP transistor 1 and V _BE2, the peak hold circuit 6 The voltage V _{103 of the} signal 103 output from is given by the following equation.

V ₁₀₃ = V _imax + V _BE1 −V _BE2 (6) In the above equation, V _BE1 and V _BE2 are given by the following equations.

V _BE1 = (kT / q) · ln (I ₁ / I _S1 ) (7) V _BE2 = (kT / q) · ln (I ₂ / I _S2 ) (8) Here, k: Portzman constant T: Absolute temperature q: Electron charge I ₁ : Current of constant current source 3 I ₂ : Current of constant current source 4 I _S1 : Reverse between base and emitter of PNP transistor 1 Direction saturation current I _S2 : reverse saturation current between base and emitter of PNP transistor 2 In the above equations (7) and (8), I ₁ = I ₂ ,
If I _S1 = I _S2 , then V _BE1 = V _BE2 , so that the voltage V _{103 of the} signal ₁₀₃ is V ₁₀₃ = V _{imax according} to the equation (6).
Becomes Thus, during up to time T _o is
The capacitor 5 is charged by the emitter current of the NPN transistor 2, the same voltage as the input voltage V ₁₀₁ is maintained. Then, when the input voltage V ₁₀₁ begins to decrease in the following time T _o, but begins to decrease also the base voltage of the NPN transistor 2, the charge accumulated in the capacitor 5 is discharged only via the constant current source 4 for,
Emitter voltage of the NPN transistor 2 is higher than the base voltage, the NPN transistor is turned off, the capacitor 5, a state in which the maximum value V _ima x the input voltage at the time T _o is maintained. The electric charge stored in the capacitor 5 (capacitance value: C ₅ ) is reduced by the time T ₁
Is the voltage V ₁₀₃ of the signal 103 at V _hold , the charge held in the capacitor 5 from the time T _o to T ₁ is expressed by the following equation via the constant current source 4 (current value: I ₂ ). It is discharged by the time constant.

T _dis = [(V _hold −V _imin ) × C ₅ ] / I ₂ (9) On the other hand, the bottom hold circuit 12 performs the same operation as the above-described peak hold circuit 6. However, the circuit configuration uses the base of the NPN transistor 7 as an input,
To have an output emitter of the PNP transistor 8, as shown in FIG. 2 (b), the input signal 102 inputted from the input signal source 20, the bottom voltage V _imin at time T _o, retained in the capacitor 11 Is done. Then, the voltage V ₁₀₄ of the signal 104 at the time T ₁ is changed to V
If you _hold, capacitor 1 over the T ₁ from time T _o
The electric charge held at 1 (capacitance value: C ₁₁ ) is discharged through the constant current source 10 (current value: I ₄ ) with a time constant represented by the following equation.

[0019] T _dis = _{[(V imin -V hold) × C} 11 ] / I ₄ ...... (10) Further, with respect to V _imin at time T _o, the base-emitter voltage V _BE7 of the NPN transistor 7, _Assuming that the base-emitter voltage V _{BE8 of the} PNP transistor 8 is
The voltage V _{104 of the} signal 104 output from the bottom hold circuit 12 is given by the following equation.

V ₁₀₄ = −V _imin −V _BE7 + V _BE8 (11) In the above equation, V _BE7 and V _BE8 are given by the following equations.

V _BE7 = (kT / q) · ln (I ₃ / I _S7 ) (12) V _BE2 = (kT / q) · ln (I ₄ / I _S8 ) (13) Here, k: Portzman constant T: Absolute temperature q: Electron charge I ₃ : Current of constant current source 9 I ₄ : Current of constant current source 10 I _S7 : Reverse saturation between base and emitter of NPN transistor 7 Current I _S8 : Reverse saturation current between base and emitter of PNP transistor 8 In the above equations (12) and (13), I ₃ = I
_{4. If} I _S7 = I _S8 , then V _BE7 = V _BE8 ,
Voltage V ₁₀₄ of the signal 104 by (11), V ₁₀₄ =
−V _imin .

The voltages V ₁₀₃ and V ₁₀₃ of the signals 103 and 104 given by the above equations (6) and (11)
₁₀₄ is input to the operational amplifier circuit 18, which operates as a subtractor as described above.
Voltage V output from output terminal 55 of operational amplifier circuit 18
_out is given by the following equation.

V _out = V ₁₀₄ −V ₁₀₃ = −V _imin −V _imax = −2V _imax (14) Therefore, in the arithmetic circuit of the present invention, Example (5)
There is no occurrence of an offset voltage as seen in the equation.

[0024]

As described above, according to the present invention, instead of forming the peak hold circuit and the bottom hold circuit by a combination of an operational amplifier and a diode, an NPN
By using a combination of the emitter follower of the transistor and the emitter follower of the PNP transistor, it is possible to eliminate the offset voltage of the output of the operational amplifier circuit to which the outputs of the peak hold circuit and the bottom hold circuit are input. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms in the present embodiment.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a diagram showing operation waveforms in a conventional example.

[Explanation of symbols]

 1,8 PNP transistor 2,7 NPN transistor 3,4,9,10,23,28 Constant current source 5,11,24,29 Capacitor 6,25 Peak hold circuit 12,30 Bottom hold circuit 13-16,31 34 resistance 17, 21, 26, 35 amplifier 18, 36 operational amplifier circuit 19, 20, 37, 38 input signal source 22, 27 diode

Claims (1)

(57) [Claims] An emitter connected to a high-potential power supply via a first constant current source, a base connected to a first input signal source, and a collector connected to a low-potential power supply; 1
A PNP transistor, a collector connected to the power supply on the high potential side, a base connected to the emitter of the first PNP transistor, and an emitter connected in parallel with a second constant current source and a first capacitor. A peak hold circuit including a first NPN transistor connected to a low-potential-side power supply via a power supply; a collector connected to the high-potential-side power supply; a base connected to the second input signal source; A second NPN transistor having an emitter connected to a power supply on the low potential side via a third constant current source; and an emitter having a high potential via a parallel circuit of a fourth constant current source and a second capacitor. Side connected to the power supply ,
The base is connected to the emitter of the second NPN transistor.
Is continued, a second collector is Ru is connected to the power supply on the low potential side
A bottom hold circuit including: a first PNP transistor; a first PNP transistor; and a calculation circuit configured to input an output of the peak hold circuit and the bottom hold circuit to perform a calculation. The base and emitter reverse saturation current values of the first and second NPN transistors are set to the same current value, and the current values of the first, second, third and fourth constant current sources are set to the same value. An arithmetic circuit characterized by: