JPS60111180A - Timer circuit - Google Patents

Abstract

PURPOSE:To realize a low power consumption of the whole timer circuit by providing a means for starting an oscillating operation of an oscillating circuit in response to an input supply signal, and stopping the oscillating operation in response to a counting completion output. CONSTITUTION:When a noise pulse Pn arrives at an input terminal IN, and only in case when a normal input signal pulse Ps arrives, an oscillating circuit 1 continues an oscillating operation extending over a necessary time. Therefore, in case of a holding state that no noise pulse Pn nor input signal pulse Ps arrives in the input terminal IN, no electric power is consumed uselessly in the oscillating circuit 1 and a frequency dividing circuit 6. In this way, a low power consumption of the whole circuit is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This paper relates to a timer circuit suitable for high-density integration, and particularly to a timer circuit that achieves low power consumption during operation.

(Background of the Invention) The present applicant has proposed various timer circuits suitable for use in vehicles, such as the one shown in Utility Model Registration Application B filed on July 12, 1980. This circuit is suitable for high-density integration and has excellent effects such as reduction in manufacturing costs.

(Object of the Invention) An object of the invention is to achieve low power consumption of such a timer circuit.

(Serialization of the Invention) In order to achieve the above objects, the present invention causes the oscillation circuit to start the oscillation operation in response to a signal supplied to the input terminal, and also starts the oscillation operation in response to the H1 number completion output. The present invention is characterized in that an oscillation operation control means for stopping the oscillation operation is provided.

(Description of Embodiments) FIG. 1 is a block diagram of a timer circuit according to the present invention, and FIG. 2 is a waveform diagram showing signal states at the center portion of FIG. 1.

First, to explain the configuration, in FIG.
is a so-called logical oscillator, and functions as an oscillation source of the reference clock pulse φ0.

The frequency dividing circuit 6 divides the reference clock pulse φ0 output from the oscillation circuit 1 to provide a first clock pulse for driving the input signal detection circuit.
clock pulse φ1 and the second clock pulse for time 7J counter drive.
A clock pulse φ2 is formed.

The input signal detection circuit 7 is of the so-called shift register type, which is known from Japanese Patent Laid-Open No. 50-23944, and is driven by the first clock pulse φ1, and is connected to the input terminal IN.
The sensor is configured to issue a predetermined detection output only when a pulse with a width greater than or equal to a certain width arrives.

The time counter 8 is a reset-type counter known in Japanese Patent Laid-open No. 40-23569 and Japanese Patent Publication No. 51-37862, etc., and performs a counting operation in response to the rise of the detection output output from the input signal detection circuit 7. At the same time, when the second clock pulse φ2 is counted a predetermined number of times, a predetermined counting completion output is issued to the output terminal OUT, and the counting operation is ended.

The oscillation operation control circuit 9 further controls the N AN in the oscillation circuit 1.
The D generator 10 is controlled by the output CON.

Next, the operation of this circuit will be explained with reference to the waveform diagram in FIG.

If we are currently waiting for an input signal, input terminal I
N is set to "O", and at this time, the output C0NT of the oscillation operation control circuit 9 is also set to (LO11).

For this reason, the NAND gate 10 in the oscillation circuit 1 is prohibited, so the oscillation circuit 1 stops its oscillation operation.

In this state, when the noise pulse Pn arrives and the input terminal IN becomes 1'' for a very short time, the output C0NT of the oscillation operation control circuit 9 also becomes 1'' in response to its rise.

Therefore, the inverter 10 in the oscillation circuit 1 is disabled, and the oscillation circuit 1 starts the oscillation operation.

In this way, when the noise pulse pn arrives at the input terminal IN, the output C0NT of the oscillation operation control circuit 9 is
The value becomes "1" for two cycles of the clock pulse φ1.

After this tC, the oscillation circuit 1 stops the oscillation operation again after two periods of the first clock pulse φ1 have elapsed.

On the other hand, a normal input signal pulse p at the input terminal IN
When s arrives, the set input S of the time counter 8 changes from "O" to 1°° with a delay of two cycles of clock pulse φ1 from the time when the input terminal IN rises from 0" to '1".
At the same time, the output terminal OUT also rises from "0" to "1".

Then, the time counter 8 receives the second clock pulse φ2.
When the predetermined number of counts are completed, the output OUT falls from "1" to O", and at the same time, the counting operation of the time counter 8 ends.

On the other hand, the output CON T i,t of the oscillation operation control circuit 9
After becoming 1'' in response to the rise of 1'' at the input terminal IN, it is continuously maintained at 1'' until the output OUT of the time counter 8 returns to NO11.

Therefore, when a normal input signal arrives, the oscillation circuit 1 starts oscillation operation in response to the rising edge of the input signal.
Thereafter, the oscillation operation continues until the time counter 8 completes the oscillation operation, and the oscillation operation ends at the same time as the time counter 8 completes the counting operation.

In this way, in the circuit of FIG. 1, the oscillation circuit 1 continues the oscillation operation for the necessary time only when the noise pulse pn arrives at the input terminal IN and when the normal input signal pulse ps arrives. Since it will continue, the input terminal I
In the standby state in which neither the noise pulse pn nor the input signal pulse ps arrives at N, power is not wasted in the oscillation circuit 1 and the frequency dividing circuit 6, thereby achieving low power consumption of the entire circuit. That's why.

In the above embodiment, as the input signal detection circuit 7, D
Although a shift 1 to register system using two stages of 70-type flip-flops has been shown, the number of cascade-connected stages of D-type flip-flops is not limited to this, and can be changed as appropriate depending on the discrimination length of the input pulse. .

(Effects of the Invention) As is clear from the description of the embodiments above, the present invention is applicable to this type of oscillation circuit 1 frequency divider circuit, shift register type input signal detection circuit, and timer circuit using a time counter. J3 prevents wasteful power consumption in the oscillation circuit and frequency divider circuit during input signal standby, thereby achieving low power consumption of the entire circuit.

Therefore, even when a large number of such timer circuits are installed in a vehicle, it is possible to prevent the battery from being over-discharged due to not driving the vehicle for a long time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a timer circuit according to the present invention, and FIG. 2 is a waveform diagram showing signal states of various parts in FIG. 1...Oscillator circuit 6...Frequency divider circuit 7...Input signal detection circuit 8...
...Time counter 9...Oscillation operation control circuit φ0...
・Reference clock pulse φ1...First clock pulse φ2...
・Second clock pulse IN...Input terminal OUT...Output terminal Patent applicant Nissan Motor Co., Ltd.

Claims (1)

[Claims] (1) An oscillation circuit that oscillates a reference clock pulse; the reference clock pulse outputted from the oscillation circuit is divided into a first clock pulse for driving an input signal detection circuit and a first clock pulse for driving a time counter. a frequency dividing circuit that forms a second clock pulse; a shift register system that is driven by the first clock pulse and emits a predetermined detection output only when a pulse of a certain width or more arrives at the input terminal lc; The input signal detection circuit starts a counting operation in response to the detection output, and
a time counter that outputs a predetermined count completion output to end the counting operation when the second clock pulse is counted a predetermined number of times; a time counter that starts an oscillation operation of the oscillation circuit in response to a signal supplied to the input terminal; and an oscillation U1 production sub-control stage which stops the oscillation operation in response to the h1 number completion output.