JP3137750B2 - Oscillation stabilization time guarantee circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an oscillation stabilization time guarantee circuit,
More specifically, the present invention relates to an LSI having an oscillation circuit and a circuit for guaranteeing the oscillation stabilization time, and particularly to an oscillation stabilization time guarantee circuit applied to a microcomputer having a stop mode.

[0002]

2. Description of the Related Art As is well known, microcomputers are used in various electronic devices in recent years. For example, when such a microcomputer is incorporated in a portable electronic device, it is particularly desirable to reduce power consumption as much as possible. Therefore, when the microcomputer is not operating (standby), the microcomputer has a stop mode (oscillation stop mode) in which the clock supplied to the microcomputer is stopped to stop the operation of the internal circuit and reduce power consumption. And other technologies are being studied.

On the other hand, a microcomputer may run away if the clock is unstable, and it is necessary to always supply a stable clock. Therefore, for example, MSM
The 66201 User's Manual states that the oscillation stabilization applied to a microcomputer having an oscillation stop mode in which the clock supplied to the microcomputer is stopped at the time of standby, and after the oscillation is released, the oscillation stabilizes, and then the clock is supplied to the microcomputer. A time guarantee circuit is disclosed.

FIG. 3 shows a conventional oscillation stabilization time guarantee circuit. As shown in the figure, the oscillation stabilization time assurance circuit 8 includes a Schmitt inverter 2 for waveform shaping, a 16-bit counter 3, a flip-flop 4, a NAND gate 5,
It comprises inverters 6 and 7.

FIG. 4 is a timing chart showing the operation of the oscillation stabilization time guarantee circuit 8 shown in FIG. The operation of the prior art will be described with reference to FIG. In the stop mode (between AB), the STOP signal becomes logic "1", the oscillation circuit 1 stops, and the 16-bit counter 3 and the flip-flop 4 are reset.

When the stop mode is released (B), ST
The OP signal becomes “0”, the oscillation circuit 1 starts oscillating,
The clock CLK is supplied to the oscillation stabilization time guarantee circuit 8.
The output waveform CLK of the oscillation circuit 1 is the Schmitt inverter 2
(C), the clock a is supplied to the 16-bit counter 3 and the 16-bit counter 3 starts counting pulses.

The 16-bit counter 3 is a counter provided to secure a time sufficient for the oscillation of the oscillation circuit 1 to stabilize. When the counter 3 starts counting and counts a predetermined number of clocks a, the Q output C of the flip-flop 4 becomes logic "1" at the falling edge of the carry output b, and passes through the NAND gate 5 and the inverters 6 and 7. A stable clock CLKOUT is output from the oscillation stabilization time guarantee circuit 8.

As described above, after the oscillation stop mode is released, the period between B and D until the oscillation circuit 1 is stabilized and the clock CLKOUT can be output again is a time for ensuring the oscillation stability.

Further, for example, Japanese Patent Application Laid-Open No. Sho 61-228725.
Japanese Unexamined Patent Publication (Kokai) No. H11-26139 discloses another conventional example of such an oscillation stabilization time guarantee circuit as an integrated circuit device. FIG. 5 shows a circuit diagram of this prior art. In this prior art, as shown in the figure, you input the output from the oscillation circuit (OSC) directly counter 70.

For this reason, in the case of this prior art, the interval between CD is longer than that in the prior art shown in FIG. 3 (the same applies between BD), and the counter 70 is used until the clock from the oscillation circuit is stabilized. Needs to count more clocks than the counter 3 of FIG. Therefore, in this prior art, a counter having a larger number of bits than in FIG.

[0011]

As described above, in the conventional oscillation stabilization time assurance circuit, if an oscillation stabilization time of 6.5 msec is to be obtained with a 10 MHz crystal oscillation circuit, for example, a 16-bit counter or more bits are required. However, there is a problem that the circuit scale becomes large. For example, in the prior art shown in FIG. 3, by increasing the hysteresis width of the Schmitt inverter 2, the output of the Schmitt inverter 2 can be obtained after the amplitude of the oscillation waveform increases.

If the output of the Schmitt inverter 2 can be obtained after the amplitude of the oscillation waveform has increased, the counter 3 can count after the oscillation of the oscillation circuit 1 is relatively stable. The number can be reduced. However, simply increasing the hysteresis width of the Schmitt inverter 2 in the circuit configuration of FIG. 3 increases the current consumption during normal operation, resulting in an increase in power consumption.

The present invention solves the above-mentioned drawbacks of the prior art, and reduces the number of bits of the counter, thereby reducing the circuit scale and reducing the power consumption during normal operation. The purpose is to provide.

[0014]

In order to solve the above-mentioned problems, the present invention operates according to the logic level of an operation control signal.
The oscillation circuit controlled by
Oscillation signal generated by the
After a predetermined time has elapsed since the operation started,
Outputs an operation clock signal based on the signal when oscillation is stable
Between the oscillation signal and the output control signal
When the output control signal is at the first logic level,
A first hiss that outputs an operation clock signal based on a signal
First waveform shaping having a hysteresis characteristic of a teresis width
Circuit for receiving an oscillation signal and counting clocks based on the oscillation signal.
Outputs a lock signal, larger than the first hysteresis width
Having a hysteresis characteristic of a second hysteresis width.
And a circuit for outputting an output control signal.
Output control signal when the oscillation circuit is in the operation stop state.
Output as a second logic level different from the first logic level
When the oscillation circuit changes from the operation stop state to the operation state
First, the counting clock signal is counted and counted up to a predetermined value.
Responsively, changing the output control signal from the second logic level to the second logic level.
A control circuit for transitioning to a logic level of 1.
is there.

In such an oscillation stabilization time assurance circuit, when the control circuit receives the stop mode signal, the second logic
Output the output control signal of
The output control signal is counted when the count clock signal reaches a predetermined value.
Signal from the second logic level to the first logic level
You.

[0016]

According to the present invention, when the stop mode is released, the second waveform shaping circuit having a large hysteresis width is used.
The counting can be started after the amplitude of the oscillation waveform increases, that is, after the oscillation is stabilized.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the oscillation stabilization time guarantee circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of an oscillation stabilization time guarantee circuit according to the present invention. The oscillation stabilization time assurance circuit 15 in the present embodiment sends a predetermined clock CLKOUT to an internal circuit of an LSI such as a microcomputer after the clock STOP from the oscillation circuit 1 is sufficiently stabilized after the STOP signal which is the oscillation stop signal is released. It is a circuit to supply.

The oscillation stabilization time guarantee circuit 15 includes two Schmitt NANDs 9 and 12 having different hysteresis widths and an n-bit counter 1 having a small number of bits.
0, a flip-flop 11 and an inverter 13 for controlling output of the NANDs 9 and 12, and an inverter 14
It consists of.

The oscillation circuit 1 connected to a crystal oscillator (not shown) is a circuit for generating a basic clock during a normal operation in which the STOP signal is logic "0". The oscillation circuit 1
It is connected to one input terminal of a Schmitt NAND 9 having a large hysteresis width and a Schmitt NAND 12 having a small hysteresis width, and outputs a basic clock CLK to these input terminals. The output terminal of the Schmitt NAND 9 is connected to the clock input terminal of the n-bit counter 10 (n <16).
The Schmitt NAND 9 is a Schmitt circuit used for stabilizing the oscillation of the oscillation circuit 1,
D12 is a Schmitt circuit for waveform shaping.

The n-bit counter 10 is a counting circuit that is reset by a STOP signal, counts pulses from the Schmitt NAND 9, and outputs a carry when the count reaches a predetermined value. n-bit counter 1
0 carry output terminal is flip-flop 1 with reset
1 clock input terminal.

The flip-flop with reset 11 is a control circuit for controlling the output of the Schmitt NANDs 9 and 12. The flip-flop 11 has a reset terminal R connected to S
The TOP signal is input to the D input terminal, and VDD is input.
During normal operation, a logic "1" is output from the output terminal Q, and a logic "0" is output from the output terminal Q during the oscillation stop and oscillation stabilization guarantee time of the oscillation circuit 1. The output terminal Q of the flip-flop 11 is connected to the other input terminal of the Schmitt NAND 12 and the input terminal of the inverter 13.

The inverter 13 is a circuit for inverting the output signal of the output terminal Q, and has an output terminal connected to the other input terminal of the NAND 9. By the inversion control of the inverter 13, the NAND 12 is selected during the normal operation, and the Schmitt NAND 9 is selected during the oscillation stop of the oscillation circuit 1 and the oscillation stabilization guarantee time.

The output terminal of the Schmitt NAND 12 is connected to the input terminal of the inverter 14, and
A predetermined clock CLKOUT is supplied from the output terminal 4 to an internal circuit such as a microprocessor as an output of the oscillation stabilization time guarantee circuit 15.

FIG. 2 is a timing chart showing the operation of the embodiment of FIG. The operation of this embodiment will be described with reference to FIGS.

In the normal operation, the output CLK of the oscillation circuit 1 is a Schmitt NAN having a small hysteresis width for waveform shaping.
D12 and the clock CLKOUT through the inverter 14
Is output as

When the stop mode is set and the STOP signal becomes logic "1" as indicated by the symbol E, the n-bit counter 10 and the flip-flop 11 are reset, and the oscillation of the oscillation circuit 1 is stopped (EF). while). As a result, the clock CLKOUT from the inverter 14 becomes logic “0”, and the clock stops.

When the stop mode is released and the STOP signal becomes "0" again as indicated by the symbol F, the oscillation circuit 1
Starts an unstable oscillation as shown in FIG.
G). At this time, the clock CLK of the oscillation circuit 1 is input to the Schmitt NAND 9 having a large hysteresis width and the Schmitt NAND 12 having a small hysteresis width. Therefore, the output of the Schmitt NAND 12 maintains the logic “1”, and the output CLKOUT of the inverter 14 maintains the logic “0”.

On the other hand, in the Schmitt NAND 9 having a large hysteresis width, since the output of the inverter 13 becomes logic "1", the input clock CLK is converted to the n-bit counter 1
However, the oscillation is unstable and the amplitude of the clock CLK is small because of a large hysteresis width.
During the period between -G, output to the n-bit counter 10 is not performed.

The oscillation of the oscillation circuit 1 is stabilized, and the clock CL
When the amplitude of K exceeds the hysteresis width of Schmitt NAND 9, the output d of Schmitt NAND 9 is input to n-bit counter 10 and starts counting. When the n-bit counter 10 overflows and the carry output e is counted and output, as shown by the symbol H, the output f of the logic "1" is output from the output terminal Q of the flip-flop 11 at its falling edge.
Is output to the other input terminal of the Schmitt 12. Thereby, the clock CLK of the oscillation circuit 1 whose oscillation is stabilized
Are the Schmitt NAND 12 for waveform shaping and the inverter 1
4 and output as a clock CLKOUT.

If the time (between F and H) for guaranteeing the oscillation stabilization is constant, the length between F and G can be set long by widening the hysteresis width of Schmitt NAND 9.
−H can be set short, and a 16-bit counter is required to obtain the same oscillation stabilization time (between F and H) in the prior art. Can be less than.

[0032]

As described above in detail, according to the present invention, when the stop mode is released, the oscillation stabilizing means having a large hysteresis width is used, so that the oscillation becomes stable after the amplitude of the oscillation waveform becomes large. Then you can start counting. Therefore, since the counting time can be shortened, a counting means having a small number of bits of the counter can be used, and the circuit scale can be reduced. Further, according to the present invention, the Schmitt circuit having a small hysteresis width can be selected without considering the oscillation stabilization time for the waveform shaping means, so that the power consumption can be reduced during the normal operation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an oscillation stabilization time guarantee circuit according to the present invention;

FIG. 2 is a timing chart showing an operation example in the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram showing an oscillation stabilization time guarantee circuit according to the related art;

4 is a timing chart showing an operation in the conventional technique of FIG. 3,

FIG. 5 is a circuit diagram showing another example of the oscillation stabilization time guarantee circuit in the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Oscillation circuit 9, 12 Schmitt NAND 10 n-bit counter 11 Flip-flop 13, 14 Inverter 15 Oscillation stabilization time guarantee circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-212417 (JP, A) JP-A-2-228105 (JP, A) JP-A-2-228106 (JP, A) JP-A-60-1985 249427 (JP, A) JP-A-4-160906 (JP, A) JP-A-3-282804 (JP, A) JP-A-63-139408 (JP, A) JP-A-61-228725 (JP, A) JP-A-57-210730 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 1/04 301 H03B 5/32

Claims (3)

(57) [Claims] An operation is performed according to a logic level of an operation control signal.
The oscillation circuit controlled by
Receiving an oscillation signal generated by the
After a predetermined time has elapsed since the
Outputs an operation clock signal based on the oscillation signal.
In the fixed time guarantee circuit, Receiving the oscillation signal and the output control signal;
When the signal is at the first logic level,
A first hysteresis for outputting the operation clock signal;
Waveform shaping circuit having hysteresis characteristic of width
When, Receiving the oscillation signal, and counting clock based on the oscillation signal.
A first hysteresis width, which outputs a clock signal.
With a hysteresis characteristic of a second hysteresis width
A second waveform shaping circuit; Outputting the output control signal, wherein the oscillation circuit
The output control signal when the road is in an inoperative state.
Output as a second logical level different from the logical level
When the oscillation circuit changes from the operation stop state to the operation state
The counting clock signal is counted and counted to a predetermined value.
The output control signal to the second logic
Control circuit for transitioning from a logic level to the first logic level
When, An oscillation stabilization time assurance circuit characterized by having: 2. The output shaping circuit according to claim 2, wherein
And the output control signal is received by the second logic level.
Output the counting clock signal when the
When the control signal is at the first logic level, the counting clock
2. The output of a clock signal is suppressed.
Oscillation stabilization time guarantee circuit. 3. The control circuit according to claim 2, wherein the operation control signal is an
Of a predetermined logic level that instructs the oscillation circuit to stop operating.
Reset state is maintained when the operation control signal is
Count operation when the logic level is different from the fixed logic level
It is possible to determine whether or not the count has reached the predetermined value.
A counting circuit that outputs a completion signal instructed by the bell,
When the operation control signal is at the predetermined logic level,
Output the output control signal as the second logic level.
And the operation control signal is maintained at the predetermined logic level.
When the completion signal is at a logic level different from
To a logic level indicating that the
The output according to the change The logic level of the control signal
Transition from the second logic level to the first logic level.
And a force control signal generation circuit.
The oscillation stabilization time guarantee circuit according to claim 1 or 2.