JPS60110066A - Data transfer control system - Google Patents

Abstract

PURPOSE:To prevent overrun by transmitting a data transfer request to a bus controller when a data transfer request is given from an input/output controller which connects an optical loop transmission line to a common bus and at the same time transmitting the inhibition signals to other input/output devices. CONSTITUTION:An input/output device controller U1 has a low transfer rate with which a floppy device FP is controlled; while an input/output device controller U2 has a high transfer rate with which a magnetic disk device MD is controlled. While various terminal devices, processors, etc. are connected to each node of an optical loop transmission line PLP for high-speed transmission of serial data. A common bus CBUS is connected to the node of the PLP via an input/output controller U3 which contains a serial/parallel conversion function. Furthermore an inhibition signal INH is transmitted to the controller U2 when a data transfer request signal REQ is transmitted from the controller U3.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to the use of a common bus in response to data transfer requests.
The present invention relates to a data transfer control system that performs data transfer by giving

Prior Art and Problems In response to data transfer requests from multiple input/output control devices connected to a common bus, the bus control device gives a permission signal, and the input/output control device that receives this permission signal transfers data via the common bus. In a data processing system that transfers data between a processor or a memory, for example, a parallel priority control method shown in FIG. 1 and a parallel priority control method shown in FIG. 2 are known. In each figure, BCTL is a bus control device, CT3US is a common bus, Ul and U2 are input/output control devices, FP is a floppy device as an input/output device, and MD is a magnetic disk device as an input/output device. Note that the processor and main memory are not shown.

In FIG. 1, the data transfer request signals REQ from the human output control devices Ul and U2 are sent to the bus control device BCT, respectively.
I, which is sent in parallel to the bus controller BC,
The TL sorts out conflicts among the data transfer request signals REQ and sends out permission signals ACK in accordance with the priority order. The input/output control device that received this permission signal ACK uses the DMA (quick left memory access) method, etc. to access the common hash CBU.
Data is transferred via S.

Also, in FIG. 2, the data transfer request signal REQ from the input/output control device U2 is sent to the bus control device BCTI via the input/output control device U1, and
The permission signal ACK from TL is sent to the input/output control device U2 via the hand saw control device U1, and when the input/output control device U2 is sending out the data transfer request signal REQ, the permission signal ACK is is transferred to the input/output control device U2. Therefore, the lotus control device B CT
The input/output control device U2 that is far from L has a high priority.

Due to recent advances in technology, the data transfer speed of magnetic disk drives is approaching the limit of the DMA capability (path switching time divided by data transfer time) via the conventional common bus CBUS. In addition, configurations that can perform high-speed serial data transfer, such as optical loop transmission lines to which various input/output devices are connected, are used, and such optical loop transmission lines are used for magnetic disk drives MD. etc., common lotus CB
It may be necessary to connect to the US via an input/output control device. However, if an optical loop transmission line for high-speed data transmission is connected to the common bus CBUS, which is already close to the limit of its data transfer capacity, the
There may be cases where MA operation etc. becomes difficult.

For example, in FIG. 1 or 2, the input/output control device U
1 and U2 each send the data transfer request signal REQ once every 3 pS, and it takes 1.5 μs to switch the 1ffl hash CBUS and it takes I It S to access via the 1 common bus CBUS. , (a in Figure 3)
) or (as shown in bl, the data transfer request is the same as 11.).
If they occur at one or almost the same time, there is a high possibility that an overrun will occur.

fal in FIG. 3 indicates a case where the data transfer request signals REQ are sent out simultaneously from the input/output control devices Ul and U2,
Assuming that CK is sent to the permission signal to the input/output device U2 with a high priority and data transfer T is performed, the input/output control device The permission signal ACK will be sent to U1, and at that point, since 3 μs or more have passed since the input/output control device U1 sent the data transfer request signals PIF, Q, the next data transfer request signal will be sent to U1. Since the timing has come to send REQ and the data transfer associated with sending the previous data transfer request signal REQ cannot be performed, the data is in an overrun state and an overrun error occurs.

+h+ in FIG. 3 indicates that the input/output control device U1 first sends out the data transfer request signal RBQ, and then the input/output control device U1 sends out the data transfer request signal RBQ.
2 sends a data transfer request signal REQ, and a permission signal ACK is sent to the input/output control device U1. In this case as well, the data transfer T of the human output control device U1 is completed. After that, a permission signal ACK is sent to the input/output control device U2, and the completion of the data transfer started by reception of this permission signal ACK is triggered by the next data transfer request signal R.
After the EQ transmission timing, an overrun state occurs.

The data transfer request signal RE is sent at a rate I- which is higher than the transfer capacity of the 1m path CBUS (path switching time 10 days transfer time).
If Q is sent, an overrun will occur in one of the input/output control devices when a conflict of data transfer requests occurs. These input/output control devices U1. In addition to U2, there are devices that use the common bus CBUS, such as processors, so if a conflict occurs between the usage cycle time of these devices and the data transfer request, the bus switching time will become even longer.

The input/output control devices Ul and U2 are provided with buffer memories of a certain capacity, but since the capacity of this buffer memory is also limited, the data transfer request signal RE
If the time from sending Q to receiving the permission signal ΔCK becomes long, buffering will not be possible and an overrun will occur.

The same data can be read again from the floppy device FP or magnetic disk device MD, so-called retry is possible, so if an overrun occurs,
Data transfer can be performed by retrying. However, if the optical loop transmission line is connected to the common bus CBUS, retries cannot be made to the optical loop transmission line, which will have a negative impact on various devices connected to the optical loop transmission line. .

From this point of view, the optical loop transmission line is connected to the common bus CBUS.
When connected to 1ffl, high-speed data transfer is possible.
It is conceivable to shorten the switching time of a common lot by providing a lot or by locally performing high-speed lot switching between devices with high transfer speeds. However, if the former configuration is adopted, it will be necessary to change the design of all conventional devices connected to the common lot, and if the latter configuration is adopted, for example, the input/output control that controls the magnetic disk device MD will need to be changed. This results in high-speed switching between the input/output controller U2 and the input/output controller that controls the connection of the optical loop transmission line, but it has the drawback of requiring a major design change of the conventional input/output controller U2.

Purpose of the Invention The present invention makes slight changes to the conventional configuration even when data is transferred by connecting an optical loop transmission line to a common bus, and prevents overruns on the optical loop transmission line side that are difficult to retry. , the purpose of which is to perform data transfer via a common bus.

Structure of the Invention The present invention provides a common i1m to which a plurality of input/output control devices are connected.
a bus control device for controlling a bus, the bus control device provides a permission signal in response to a data transfer request from the plurality of input/output control devices, and the input/output control device receiving the permission signal transmits the data transfer request via the common bus. In a data transfer control method in which data is transferred using a bus, when a data transfer request is made from a specific input/output control device such as an input/output control device that connects an optical loop transmission line to the common bus, data is transferred to the lotus control device. The input/output control device that sends the request signal and also sends a prohibition signal to other input/output control devices, and receives the prohibition signal,
This is to wait for the sending of a data transfer request signal, and an embodiment will be described in detail below.

Embodiment of the Invention FIG. 4 is a block diagram of a main part of an embodiment of the present invention, and shows a case where a priority control method is applied.

The input/output control word MU1 controls the floppy device FP, and has a relatively low transfer rate. The input/output control device U2 controls the magnetic disk device MD,
The transfer rate is relatively high. In addition, PLP indicates an optical loop transmission line, and as is well known, an optical loop transmission line is used to connect various terminal devices, processors, etc. to each node and transmit serial data at high speed. The common lotus CBUS is connected via the control device U3. This input/output control device U3 converts the serial data on the optical loop transmission line PLP into parallel data and sends it to the common bus CBUS, converts the parallel data from the common bus CBUS into serial data, and converts the serial data from the optical loop transmission line PLP into serial data.
This includes a function to send data to LP. Also, when the input/output control device U3 sends out the data transfer request signal REQ, it sends the inhibition signal INH to the input/output control device U2 having a high transfer rate.

In the case of the optical loop transmission line PLP, as shown in the previous example, retries are difficult, so until the data transfer from the optical loop transmission line PLP is completed, the input/output control device U2 with a high transfer rate is is for prohibiting the sending of the data transfer request signal REQ.

When this input/output control device U2 receives the inhibit 1F signal I N H, it waits to send the data transfer request signal REQ even if there is a data transfer request, and transmits the data transfer request signal REQ to the input/output control device U3.
When the bus control device BCTL sends out the permission signal ACK in response to the data transfer request signal REQ sent by the bus control device BCTL, the data is transferred to the input/output control device U2 via the input/output control device U1, and its input/output control is performed. The device U2 also transfers the data as is to the input/output control device U3. That is, since the input/output control device U2 can retry, the input/output control device U3
The input/output control unit 9U2 performs data transfer with priority.
If an overrun occurs, the processor (not shown)
The system causes a retry by reading the status information or by interrupting by other means.

Note that it is also possible to apply the inhibition signal INH to the input/output control device U1 to inhibit sending of the data transfer request signal REQ, but in this embodiment, since the transfer rate of the floppy device FP is relatively low, the inhibition signal INH is A configuration in which INH is not added is not shown.

FIG. 5 is an explanatory diagram of the operation of the embodiment of the present invention, and the period ■
In this case, there is no data transfer request from the optical loop transmission line PLP side, and the input/output control device 01. Permit signal AC in response to data transfer request signal REQ from U'2
K is sent from the bus controller BCT■7, and the permission signal A
The input/output control device that received the CK is the common lotus CBLIS.
Data is transferred via the . In addition, the input/output control device U1 first sends out data transfer request signals RF and Q,
When the permission signal ACK is received, the permission signal AC is sent to the data transfer request signals RP and Q from the input/output control device U2.
K will be received after the input/output control device U1 completes data transfer.

During period ■, the data transfer request signal REQ is sent from the input/output control device U3, and at the same time the prohibition signal T N H is sent out.
is sent. This prohibition signal r N H is continuously transmitted until the transfer of the final data is completed, and the input/output control device U2, which has received this prohibition signal T N tI, waits for the transmission of the data transfer request signal REQ. Since the inhibition signal lN11 is not applied to the input/output control device U1, when the data transfer request signal REQ is sent, the input/output control device U1
At the end of the data transfer in step 3, the permission signal ACK is applied and the data transfer is performed. In this case, the input/output control device T
Even if a data transfer request is generated from J3, the transfer rate of the floppy device FP is low, so the input/output control device U
It is sufficient that the capacity of the buffer memory provided in 3 is small.

As shown by the dotted line during this period H, even if a data transfer request occurs in the input/output control device U2, the transmission of the data transfer request signal REQ is prohibited until the inhibition signal TNH disappears, and the transmission of the data transfer request signal REQ is prohibited until the inhibition signal INH disappears. The data transfer request signal RE'Q will be sent out in the subsequent period (3).

At this time, if no overrun has occurred in the input/output control device U2, data transfer is performed upon reception of the permission signal ACK, and if an overrun has occurred, a retry operation is performed.

The crowd control device U3 is provided with means for continuously sending out a prohibition signal T N H from sending out the data transfer request signal REQ until identifying the final data of the transfer data, and In the control device U2, the prohibition signal I
Due to NH, it is sufficient to provide means for blocking the sending of the data transfer request signal REQ. When the input/output control device U2 is not transferring data, the permission signal ACK from the bus control device BCTL is directly transferred to the next input/output control device LJ3, so that the input/output control device U3 transfers data. If the transfer request signal REQ is sent and the input/output control WffUl is not transferring data, the permission signal ACK from the lotus control device B C"L will be transferred to the human output control device U3.

As described above, by only slightly changing the conventional configuration, it is possible to connect the optical loop transmission line PLP to the common bus CBUS via the input/output control device U3 and perform data transfer. In addition, the present invention can be applied not only to a priority control method but also to a parallel priority control method, in which an optical loop transmission line PL P is connected to an input/output control device with a high transfer rate. When the data transfer request signal REQ is sent from the human output control device U3, the prohibition signal IN
H can be sent.

Advantages of the Invention As explained above, the present invention provides a common bus CBU S
Input/output control device 1rU1. A floppy device FP, a magnetic disk device MD, etc. are connected via U2, and both are 1tT.
In a system that transfers data via the I bus CBUS, the optical loop transmission line PLP is connected to the input/output control device U3.
It is possible to perform data transfer by connecting to the common lotus CBUS via the common lotus controller BCTI, and sends a data transfer request signal REQ from such a specific input/output control device U3 to the lotus controller BCTI. Input/output control device U
2, the inhibition signal INH is sent to
The input/output control bag Fi' u 2 that has received the data waits for the sending of the data transfer request signal REQ, and is connected to the input/output control device U connected to the conventional common lot bus CB US.
2 is changed by the data transfer request signal I? by the inhibit signal INH. The optical loop transmission line P is simply added with a configuration that prevents the transmission of EQ, and it is difficult to retry ff1tt.
Data transfer from the L P via the common bus CBU S can be performed without causing an overrun. That is, there is an advantage that data transfer can be performed on the optical loop transmission line P L P via the 1ffl hash CB tJ S with a slight modification of the conventional configuration.

[Brief explanation of drawings]

Figures 1 and 2 show the conventional common bus control =y+
A block diagram of the main parts of the fE column priority control system and the priority control system shown in FIG. is an explanatory diagram of the operation of the embodiment of the present invention. BCTL is a bus control device, CBUS is a common bus, Ul,
U2. U3 is a human output control device, FP is a floppy device,
MD is a magnetic disk device, PLP is an optical loop transmission line, REQ is a data transfer request signal, ACK is a permission signal, I
NH is a prohibition signal. Patent Applicant Fujitsu Co., Ltd. Representative Patent Attorney Akio Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 1 Figure 2 Figure 3 (a) (b) Figure 4

Claims (1)

[Claims] A bus control device that controls a common bus to which a plurality of input/output control devices are connected is provided, the bus control device gives a permission signal to a data transfer request of the plurality of input/output control devices, and receives the permission signal. In a data transfer control method in which an input/output control device transfers data via the common bus, when a data transfer request is made from a specific human output control device,
A data transfer request signal is sent to the bus control device, and a prohibition signal is sent to another input/output control device, and the input/output control device that receives the prohibition signal waits for sending the data transfer request signal. Characteristic data transfer control method.