JPS59163662A - Access system of memory - Google Patents

Access system of memory

Info

Publication number
JPS59163662A
JPS59163662A JP3734883A JP3734883A JPS59163662A JP S59163662 A JPS59163662 A JP S59163662A JP 3734883 A JP3734883 A JP 3734883A JP 3734883 A JP3734883 A JP 3734883A JP S59163662 A JPS59163662 A JP S59163662A
Authority
JP
Japan
Prior art keywords
signal
access
storage device
line
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3734883A
Other languages
Japanese (ja)
Inventor
Masao Kato
正男 加藤
Toshihiro Okabe
岡部　年宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3734883A priority Critical patent/JPS59163662A/en
Publication of JPS59163662A publication Critical patent/JPS59163662A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To attain a high-speed access to a memory with a small quantity of hardware by transmitting a permission signal for use to an access device from a memory in case plural access devices request accesses at a time. CONSTITUTION:If the request signals REQ are transmitted at a time from two CPU1, a memory 2 sends a permission signal ACP for use if bus only to either one of these CPU1 and turns on a BUSY signal. The CPU1 received the ACP signal and at the same time transmits continuously the address/write data information, etc. to a bus signal line 3. While the CPU1 which received no APC signal detects the ON state of the BUSY signal and turns off the REQ signal as well as discontinues the transmission of information to the line 3. As a result, the information on only one CPU1 is delivered onto the line 3 and the memory 2 can work with use of said information.

Description

【発明の詳細な説明】 本発明は記憶装置のアクセス方式に関し、詳しくは、複
数のアクセス装置（処理装置）で記憶装置を共有する情
報処理装置における記憶装置のアクセス方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device access method, and more particularly to a storage device access method in an information processing device in which a storage device is shared by a plurality of access devices (processing devices).

〔従来技術〕[Prior art]

情報処理装置では、性能上記憶装置をいかに高速にアク
セスするかが最も重要な要素である。一般に、記憶装置
をアクセスするには以下の手順を踏む。In an information processing device, the most important factor in terms of performance is how quickly the storage device can be accessed. Generally, the following steps are taken to access a storage device.

（１）記憶装置アクセス要求元装置から、記憶装置に対
してアクセス要求信号（以丁几Ｅ（送信号と略す）の発
信。(1) Sending an access request signal (abbreviated as transmission signal) from the storage device access requesting device to the storage device.

（２）記憶装置からのアクセス許可信号（以下ＡＣＰ信
号と略す）の受信。(2) Receiving an access permission signal (hereinafter abbreviated as ACP signal) from the storage device.

（３２記憶装置をアクセスするためのアドレス情報、書
込みデータ情報等の送１ぎ。(Transmission of address information, write data information, etc. for accessing the 32 storage device.

＋４Ｊ　　記憶装置からの杭出しデータ情報、および記
憶装置アクセス動作終了報告信号（以丁ＥＮＤ１ｇ号と
略す）の受信。+4J Reception of stakeout data information from the storage device and storage device access operation completion report signal (abbreviated as END1g).

同一の記憶装置を複数の装置がアクセスする様な情報処
理装置において、高速性能が要求される大杉の装置では
、各アクセス要求元装置と記憶装置を固有の信号線にて
接続し、ＲＥＱ信号の発信と同時にアドレスｔ＃報、書
込みデータ情報を送信する方式がとられ、記憶装置アク
セスの高速化が計られている。In information processing equipment where multiple devices access the same storage device, Osugi's device requires high-speed performance, and connects each access request source device and storage device with a unique signal line, and transmits the REQ signal. A system is adopted in which address t# information and write data information are transmitted at the same time as the transmission, thereby speeding up the access to the storage device.

しかし、小形の情報処理装置では、ノ・−ドウエア量を
少なくすることが重要であり、複数のアクセス要求元装
置と記憶装置を共通の信号線で接続する方式がとられる
。この方式では、複数の装置からの清報が衝突するのを
さけるために、記憶装置からｆｆ０Ｔされた装置のみが
信号＠を使用する方式としなければならない。このため
、＋１）　ＲＥ　＋込信号の発信、（２ＬＡｃＰ信号の
受信、（３）アドレス情報。However, in a small information processing device, it is important to reduce the amount of node hardware, and a method is adopted in which a plurality of access request source devices and storage devices are connected through a common signal line. In this method, in order to avoid conflicting information from multiple devices, only the device that has been ff0Ted from the storage device must use the signal @. Therefore, +1) transmission of RE + signal, (reception of 2LAcP signal, (3) address information.

書込みデータ情報の送信という順序で処理を遂行せざる
全得なく、前者の方式にくらべ、記憶装置アクセス時間
が増加するという欠点があった。This method has the disadvantage that the processing must be performed in the order of sending the write data information, which increases the time required to access the storage device compared to the former method.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、少ない・・−ドウエア量で記憶装置の
アクセスを高速に行うことのできるアクセス方式を提供
することにある。An object of the present invention is to provide an access method that can access a storage device at high speed with a small amount of hardware.

〔発明の概要〕[Summary of the invention]

本発明は、記憶装置と複数のアクセス装置でデータの授
受を行うバス線は共通化すると共に、アクセス装置から
記憶装置へのリクエスト線と記憶装置からアクセス装置
へのバス使用許可ｆｇ対線は個々に結ぶ。そして、複数
のアクセス装置電が同時にアクセス要求する頻度は低い
ことを利用して、アクセスを要求するアクセス装置はリ
クエスト（几ＥＱ）信号をリクエスト線に送出すると同
時に、このＲＥ　Ｑ信号に付随する情報をバス線に送出
する。これに対して、記憶装置はａ　Ｅ　１．Ｑ信号で
応答し゛Ｃアクセスを要求するアクセス装置にバス使用
許可（ＡＣＰ）信号を送出する。父、複数のアクセス装
置が同時に１ｔＦＪＣン倍号を送出してアクセスを要・
Ｒする場合、バス線上の情＠が衝突することになるので
、記ｔｋｉ、装置は１つのアクセス装置にＡＣＰ１ｇ号
を送出し、ＡＣＰ信号を受信できなかったアクセス装置
はＲＥ　Ｑ　ＩＮ号をオフにすると共にバス線への情報
の送出を中止する。In the present invention, a bus line for exchanging data between a storage device and a plurality of access devices is shared, and a request line from the access device to the storage device and a bus use permission fg pair line from the storage device to the access device are individually connected. Tie to. Taking advantage of the fact that the frequency with which multiple access devices request access at the same time is low, the access device requesting access sends a request (几EQ) signal to the request line, and at the same time transmits the information accompanying this REQ signal. is sent to the bus line. On the other hand, the storage device is a E 1. It responds with the Q signal and sends a bus permission (ACP) signal to the access device requesting the C access. Father, when multiple access devices simultaneously send out 1tFJC and request access.
If R, the information on the bus line will conflict, so the device sends the ACP1g signal to one access device, and the access device that cannot receive the ACP signal turns off the RE Q IN signal. At the same time, the transmission of information to the bus line is stopped.

〔発明の実施例〕[Embodiments of the invention]

第１図は本発明の一実施例を示す。第１図において、複
数の中央処理装置（以下、ＣＰＵと略す）１は、各装置
共通のバス信号縁；うで記憶装置２と接続されている。FIG. 1 shows an embodiment of the invention. In FIG. 1, a plurality of central processing units (hereinafter abbreviated as CPU) 1 are connected to a storage device 2 at a bus signal edge common to each device.

本バス伯対線８は、記憶装置アクセス時のアドレス、４
込みデータ、読出しデータの情報か転送される信号線で
ある。また、各ＣＰＵ１は個々に記憶装＋ｔ２と複数本
の１ぎ対線４で接続されている。本信号線４はＲＥｌ、
Ｑ信号、ＡＣｅｌＢ号、ＥＮＤ信号からなる。This bus pair line 8 is the address 4 when accessing the storage device.
This is a signal line through which information such as input data and read data is transferred. Further, each CPU 1 is individually connected to a storage device +t2 by a plurality of single-pair wires 4. This signal line 4 is REl,
It consists of a Q signal, an ACelB signal, and an END signal.

現在記憶装置が動作中であり、新たなアクセス要求が受
付けられない状態にあることを示す信号（以′ＦＢＵＳ
Ｙ信号と略す）は、信号線５により複数のＣＰＵ１に共
通に接続されている。A signal indicating that the storage device is currently in operation and cannot accept new access requests (abbreviated as 'FBUS').
(abbreviated as Y signal) is commonly connected to a plurality of CPUs 1 via a signal line 5.

記憶装置２は、記憶回路２１と、ＣＰＵ１とのデータ授
受制御、各種制御信号の授受、および記憶回路２１を制
■する制御回路２２により構成されている。The storage device 2 includes a storage circuit 21 and a control circuit 22 that controls data exchange with the CPU 1, exchanges various control signals, and controls the storage circuit 21.

次に第２図及び第８図のタイムチャートにより第１図の
動作を説明ず妬。Next, I am jealous that I have not explained the operation in Figure 1 using the time charts in Figures 2 and 8.

第２図は被数のＣＰＵＩのうち、１台のＣＰＵのみから
記憶装置のアクセス要求が発せられた場合のタイムチャ
ートである。今、ＢＵＳＹ信号が“オフ”状態（アクセ
ス要求受付は可能状態）にある時、ＣＰＵ１に記憶装置
アクセス要因が発生したならば、このＣＰＵＩは記憶装
ｆｆ１２に対して）ＩＥＱ（ｉ−号音発信すると同時に
、バス信号線８（図中ではＢＬＩＳ）に対してアドレス
情報を、督込み動作の場合には畜込みデータ情報を送出
する。FIG. 2 is a time chart when a storage device access request is issued from only one CPU among the CPUIs. Now, when the BUSY signal is in the "off" state (access request acceptance is possible), if a storage device access factor occurs in CPU1, this CPU will send an IEQ (i-tone) to the storage device ff12. At the same time, address information is sent to the bus signal line 8 (BLIS in the figure), and in the case of stocking operation, stored data information is sent.

ＲＥ　１．Ｑ信号を受信した記憶装置２は、ＡＣＰ信号
をアクセス元のＣＰＵＩに発イぎすると同時に、ＢＵＳ
Ｙｊｉ号を”オン″状態（アクセス要求受付は不可状態
）に設定し、かつバス信号線８上のＴ’ｆｆ報を記憶す
る。RE 1. The storage device 2 that received the Q signal issues an ACP signal to the access source CPUI, and at the same time sends the BUS
The Yji signal is set to the "on" state (access request reception is disabled), and the T'ff information on the bus signal line 8 is stored.

ＡＣＰ乍号を受信したＣ　ＰＵ　ｌはｆ（、Ｅ　Ｑ信号
を”オフ”とし、記憶装置２の動作長Ｔを待つ。記憶装
置２けアクセス要求の処理が終了すると、アクセス要求
元のＣＰＵＩに対してＥＮＤ信号を発信するとともに、
アクセス要求が読出し動作時には、読出しデータをバス
信号線８上に送出する。Upon receiving the ACP code, the CPU 1 turns off the EQ signal and waits for the operation length T of the storage device 2. When the processing of the 2-storage device access request is completed, the At the same time as sending an END signal to
When the access request is a read operation, read data is sent onto the bus signal line 8.

Ｆ３ＮＤ信号を受信したＣＩ’Ｕ１は、アクセス要求が
読出し動作時には、バス１３号線３上の情報を入手した
後、記憶装置アクセス動作を終了し、次の動作に移る。When the access request is a read operation, the CI'U1 that has received the F3ND signal completes the storage device access operation after obtaining the information on the bus 13 line 3, and moves on to the next operation.

以上説明した様に、個々のＣＰＵ１は、他のＣＰＵ１の
状態に関係なく、記憶装置２からの１３０８Ｙ信号のみ
を参照してＬ（、ｇＱ倍号を発信し、Ａｃ１１ｇ号を待
つことなくアドレス、簀込みデータをバス信′ｇｊ線８
上に送信する方式である。複数のＣＰＵ１が同時に記憶
装置２をアクセスしてパス１ｇ号＃８上で情報の衝突が
発生しないかぎりは、複数のＣＰＵ１が、個々に記は装
置２との間にバス信号線８を保持する方式と同等の性能
を得ることができる。多くの場合、複数のＣＰＵ１が同
時にアクセスを要求する頻度は高くないため、単一のＣ
ＰＵがアクセスを要求する場合は、記憶装置のアクセス
を高速に行うことができる。As explained above, each CPU 1 refers only to the 1308Y signal from the storage device 2 and transmits the L(, gQ double number, and addresses, without waiting for the Ac11g signal, regardless of the status of other CPUs 1. Transfer the stored data to the bus 'gj line 8
This is a method of transmitting data upwards. Unless multiple CPUs 1 access the storage device 2 at the same time and an information conflict occurs on path 1g #8, the multiple CPUs 1 individually maintain the bus signal line 8 between them and the device 2. It is possible to obtain the same performance as the method. In many cases, multiple CPUs 1 do not request access at the same time, so a single
When the PU requests access, the storage device can be accessed at high speed.

第８図は同時に２台のＣＰＵ１が記憶装＃２のアクセス
を開始した時の動作を示すタイムチャートである。ＢＵ
ＳＹ信号が”オフ”状態時に、２台のＣＰＵ１より同時
にＲＥＩン１ぎ号が発信された場合、２台のＣＰＵ共に
几ＥＱ信号と同時にバス信号線８上にアクセス情報を送
出するので、２台のＣＰＵからの情報が衝突し、本バス
信号線８上の情報は使用不可となる。この時、記憶装置
２は２つのＲＥＱ倍信号ＲＥＱＩ、およびＲＥＱ２）が
゛オン”となっていることを検出し、どちらか一方のＣ
ＰＵＩに対してのみＡＣＰ信号を発信し、かつＢＵＯＹ
信号を６オン”とする。FIG. 8 is a time chart showing the operation when two CPUs 1 start accessing the storage device #2 at the same time. B.U.
If the REI signal is sent simultaneously from two CPUs 1 while the SY signal is in the "off" state, both CPUs send access information on the bus signal line 8 at the same time as the EQ signal. The information from the two CPUs collides, and the information on the main bus signal line 8 becomes unusable. At this time, the storage device 2 detects that the two REQ multiplied signals REQI and REQ2) are turned on, and one of the
Sends ACP signal only to PUI, and BUOY
Set the signal to 6".

ＡｃＰ１百号を受信しだＣＰＵ１はＲＥＱ、信号を１オ
フ”とし、かつバス信号線８に対してアドレス、督込み
データ情報等の送出を継続する。一方、ＡＣＰ信号が受
信できなかったＣ’　Ｐ　Ｕ　ｌは、ＢＵＳＹ信号が”
オン”になった事を検出し、ＦＬＥＱ信号を”オフ”と
し、かつバス信号線８に対する１青報の送出全中止する
。これによって、バスＩｖＳＢ上ＫＵ唯一のＣＰＵＩの
１青報が出力されている状態になり、本情報を使用して
記憶装置２が動作可能となる。記憶装置２の動作が終了
したならば、ＲＥＩン信号を受信した方のＣＰＵ１に対
してＥＮＤ１＠号を発信した後、ＢＵＳＹ偏号を信号フ
・とする。Upon receiving AcP100, the CPU 1 turns the REQ signal 1 off, and continues to send the address, command data information, etc. to the bus signal line 8. On the other hand, the CPU 1, which cannot receive the ACP signal, P U l is BUSY signal.
It detects that the FLEQ signal is turned on, turns the FLEQ signal off, and stops sending out all 1 green alerts to bus signal line 8. As a result, 1 green alert of KU's only CPUI on bus IvSB is output. The storage device 2 becomes operational using this information.When the operation of the storage device 2 is completed, an END1@ signal is sent to the CPU 1 that received the REI-in signal. After that, the BUSY decoding is set as the signal F.

ＲＥ　Ｑ信号が受付けられなかった方のＣＰＵ１はＢＵ
ＳＹ倍号が゛オフ”となった事を千莢出し、再ｖａＥ＋
込信号を発信する。以降第２図で示したのと同様に処理
されていく。The CPU1 that did not receive the REQ signal is BU.
I took out the fact that the SY double number was "off" and re-vaE+
Sends an incoming signal. Thereafter, processing is performed in the same manner as shown in FIG.

したがって、複数台のＣＰＵ１が同時にＲ，ＥＱｌに号
を発１ｇしても、記憶装置１２で指定される受付は優先
順序指示により順序付けされた装置毎に逐次記憶装置ア
クセス動作を処理することができる。Therefore, even if multiple CPUs 1 issue signals to R and EQl at the same time, the reception designated by the storage device 12 can sequentially process storage device access operations for each device ordered by the priority order instruction. .

本実施例では、記憶装置アクセス元の装置を中央処理装
置としたが、記憶装置２とのインタフェース１ぎ号を合
致させれば、データ転送装置等にも使用できる方式であ
ることは明らかである。In this embodiment, the device that accesses the storage device is the central processing unit, but it is clear that this system can also be used for data transfer devices, etc., as long as the interface number with the storage device 2 matches. .

また本実施例において、バス１百号線３はアドレス情報
、データ情報用の別個のものを持つものとし、最も高速
なデータ転送が可能な方式としているが、アドレス情報
、および書込データ情報を時系列に制［有］し、同一の
バス線にて悄＠を転送する方式にすれば、さらにバス信
号線の本数を少なくできることも明らかである。In addition, in this embodiment, the bus 100 line 3 has separate ones for address information and data information, which is a method that allows for the fastest data transfer, but the address information and write data information are It is clear that the number of bus signal lines can be further reduced if the system is controlled in series and the yu@ is transmitted over the same bus line.

〔発明の効果〕〔Effect of the invention〕

以上説明したごとく本発明によれば、記憶装置と記憶装
置をアクセスする複数の装置間を同一のバス線で接続し
、同時に複数の装置から記憶装置に対してアクセス要求
が発生していなければ、本バス線をあたかも各装置固有
のバス線のごとく使用できるだめ、従来のバス線方式の
記憶装置アクセス方式に比較し、高速に記憶装置をアク
セスすることが可能となり、従来のバス線方式の・・−
ドウエア量を増加させることなく、記憶装置アクセス性
能を向上させることができる。As explained above, according to the present invention, if a storage device and a plurality of devices that access the storage device are connected by the same bus line, and access requests to the storage device are not issued from the plurality of devices at the same time, Because this bus line can be used as if it were a bus line specific to each device, it is possible to access the storage device at a higher speed compared to the conventional bus line method for accessing storage devices.・−
Storage device access performance can be improved without increasing the amount of hardware.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示すブロック図、第２図及
び第３図は第１図の動作を説明するタイミング図である
。 １・・・中央処理装置、２・・・記憶装置、２１・・・
記憶回路、２２・・・記憶制御回路、８・・・バス信号
線、４・・・信号線、５・・・１ｇ号線。 代理人　弁理士　　高　橋　明　　大FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are timing diagrams explaining the operation of FIG. 1. 1...Central processing unit, 2...Storage device, 21...
Memory circuit, 22... Memory control circuit, 8... Bus signal line, 4... Signal line, 5... 1g line. Agent Patent Attorney Akihiro Takahashi

Claims (1)

【特許請求の範囲】[Claims] （１）記憶装置と複数のアクセス装置との間を、個々の
アクセス装置から記憶装置ヘリクエストを出す信号線（
リクエスト信号線）と、記憶装置から個々のアクセス装
置へバス使用許可信号を出す信号線（バス使用許可信号
線）と、両装置間でデータの授受を行う共通のバス線と
で結び、アクセスを要求するアクセス装置は、リクエス
ト信号を該当リクエスト線に送出すると同時に該リクエ
スト信号に付随する情報を上記バス線に送出し、記憶装
置は、上記リクエスト信号に応答して、上記アクセスを
要求するアクセス装置にバス使用許可信号を送出す不記
憶装置のアクセス方式であって、複数のアクセス装置が
同時にそれぞれ該当リクエスト信号線にリクエスト信号
を送出してアクセスを要求する時、上記記憶装置は１つ
のアクセス装置にバス使用許可信号を送出し、該バス使
用許可信号を受信できなかった他のアクセス装置は、該
当リクエスト信号をオフにすると共に上記バス線への情
報の送出を中止することを％徴とする記憶装置のアクセ
ス方式。(1) A signal line between the storage device and multiple access devices that sends requests from each access device to the storage device (
The request signal line), the signal line that sends a bus use permission signal from the storage device to each access device (bus use permission signal line), and the common bus line that exchanges data between both devices. The access device making the request sends a request signal to the corresponding request line and at the same time sends information accompanying the request signal to the bus line, and in response to the request signal, the storage device sends the request signal to the corresponding request line. This is an access method for a non-storage device that sends out a bus use permission signal to a bus, and when multiple access devices simultaneously send request signals to the corresponding request signal lines to request access, the storage device is connected to one access device. The other access devices that have not received the bus use permission signal are required to turn off the corresponding request signal and stop sending information to the bus line. Storage device access method.
JP3734883A 1983-03-09 1983-03-09 Access system of memory Pending JPS59163662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3734883A JPS59163662A (en) 1983-03-09 1983-03-09 Access system of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3734883A JPS59163662A (en) 1983-03-09 1983-03-09 Access system of memory

Publications (1)

Publication Number Publication Date
JPS59163662A true JPS59163662A (en) 1984-09-14

Family

ID=12495061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3734883A Pending JPS59163662A (en) 1983-03-09 1983-03-09 Access system of memory

Country Status (1)

Country Link
JP (1) JPS59163662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02250136A (en) * 1989-01-20 1990-10-05 Pfu Ltd Bus control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02250136A (en) * 1989-01-20 1990-10-05 Pfu Ltd Bus control system

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