JPS60109297A - Method of producing printed board - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a conductivity test 5M 2 for the inner core of a printed board.
The present invention relates to a method of manufacturing a printed board, which is particularly suitable for reducing the number of man-hours required for inner layer core continuity testing of a printed board by creating /l/*-rules on the entire grid.

[Background of the invention]

In conventional printed board manufacturing, as shown in FIG. 5, an inner layer core (C) is created from a base material (α).

The inner layer core in (C) has a circuit in the state shown in Figure 1, and in order to test the continuity of this pattern, it is necessary to conduct a continuity test from both sides as shown in Figure 6, and therefore it has logic. Continuity testing of the inner core takes a lot of time, and there is a problem in that the time required for the printed circuit board to be densified increases.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned conventional problems, and to complete the continuity test of the inner layer core of the printed board at once, there is a method for manufacturing a printed board in which through-holes are provided on all the grids during the manufacture of the inner layer core. It is in a place where we provide.

[Summary of the invention]

A feature of the present invention is that in order to complete the continuity test of the inner core at once, through-holes for continuity testing are provided on the entire grid during the production of the inner core, which allows the continuity test of the front side to be performed at the same time.

Continuity tests can also be performed on the back side using through holes for continuity tests.

[Embodiments of the invention]

Next, embodiments of the present invention will be described in detail using the drawings.

FIG. 5 shows a conventional printed board manufacturing method, and FIG. 6 shows a printed board manufacturing method of the present invention. In FIG. 6, holes are made in the inner layer core base material 7 with the inner layer core material copper foil 6 pasted on both sides by a known method, and through holes 2 for continuity testing are created on the entire grid by copper plating by a known method. . Thereafter, the inner layer line 1 is created by a known method, and in the next step, a continuity test of the inner layer core is performed. After conducting the continuity test, the layers are laminated and bonded using a known method. After lamination and adhesion, holes 10 for through-holes are bored by a known method. At this time, since the through-hole hole 2 for continuity testing has a smaller diameter than the through-hole 10, it is removed when the through-hole hole 20 is drilled. After drilling the through holes, a printed board having multilayer inner layer circuits is obtained by a known method.

The difference between the continuity test performed in the embodiment and the continuity test performed by the conventional manufacturing method will be explained with reference to FIGS. 5 and 4.

Figure 3 shows the conventional inner layer core continuity test, but when viewed from the direction of (α), the continuity tester test pin 50 connection at @ can be detected, but the connection at 0θ cannot be detected. Therefore, a continuity test is required from the back side as shown in (b). This is because in the completed printed board, the connection will be made from ■ to θ through the through-hole. In the printed board manufacturing method of the present invention, as shown in FIG. 4, in the continuity test of the inner layer core, the connection of ■@θ can be detected at once through the continuity test through hole 2'll'.

〔Effect of the invention〕

According to the present invention, the following effects can be obtained.

1. The through-holes for continuity testing provided on all the grids make it possible for the inner layer core to pass through the grid.

It is also possible to perform a functional test on circuits with a single continuity test, reducing the number of man-hours required for continuity testing.

2. In conventional continuity tests, the continuity pin contacts at one point at the tip, but according to the present invention, the contact surface of the continuity pin is on the circumference of the continuity test through hole, improving the accuracy of continuity tests. .

[Brief explanation of the drawing]

FIG. 1 is a plan view of a conventional inner core material, FIG. 2 is a plan view of an inner core material according to an embodiment of the present invention, FIG. 3 is an explanatory diagram of a conventional inner core material conduction test, and FIG. 4 is an explanatory diagram of the continuity test method according to the present invention, No. FIG. 5 is an explanatory diagram showing conventional printed board manufacturing, and FIG. 6 is an example of the printed board manufacturing method according to the present invention. It is an explanatory view showing an example. 1: Inner layer line, 2: Through hole for inner layer continuity test, 6:
Inner layer pad, 4: Inner layer core material, 5: Continuity tester inspection pin, 6: Inner layer core material copper foil, 7: Inner layer core base material, 8 Niblipreg, 9: Outer layer core base material, 10: Hole for through hole. Figure 1 Figure 2 Figure 5 Figure 5 Figure Δ Figure

Claims (1)

[Claims] 1. In a method for manufacturing a printed circuit board having a multilayer inner layer circuit, when conducting a continuity test on the inner layer circuit, through-holes and pads are placed on the entire grid so that a continuity test on both sides can be performed by conducting a continuity test on one side. A method for manufacturing a printed board, characterized in that the through hole is smaller than a through hole formed after laminating multilayer inner layer circuits.