JPS63202997A - Inspection of multilayer interconnection - Google Patents
Inspection of multilayer interconnectionInfo
- Publication number
- JPS63202997A JPS63202997A JP3496787A JP3496787A JPS63202997A JP S63202997 A JPS63202997 A JP S63202997A JP 3496787 A JP3496787 A JP 3496787A JP 3496787 A JP3496787 A JP 3496787A JP S63202997 A JPS63202997 A JP S63202997A
- Authority
- JP
- Japan
- Prior art keywords
- multilayer wiring
- wiring
- insulating substrate
- pad
- inspection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007689 inspection Methods 0.000 title description 6
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 238000009713 electroplating Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 description 17
- 239000010409 thin film Substances 0.000 description 8
- 239000000523 sample Substances 0.000 description 7
- 238000001514 detection method Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 229910001120 nichrome Inorganic materials 0.000 description 2
- 101150108558 PAD1 gene Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
多層配線の内部配線の断線を検査する方法であり、
絶縁基板に形成し該内部配線と一端が接続するスルーホ
ールと、該スルーホールの他端に接続する導体層を介し
、電気めっき手段で該断線を検知することにより、
目視できない該断線の検査を容易にしたものである。[Detailed Description of the Invention] [Summary] A method for inspecting disconnections in internal wiring of multilayer wiring, which includes: a through hole formed in an insulating substrate and connected to the internal wiring at one end; and a through hole connected to the other end of the through hole. By detecting the disconnection using electroplating through the conductor layer, inspection for the disconnection, which cannot be visually observed, is facilitated.
本発明は、絶縁基板に形成した多層配線の内部断線を検
知する検査方法の改良に関する。The present invention relates to an improvement in an inspection method for detecting internal disconnections in multilayer wiring formed on an insulating substrate.
第３図は多層配線の上にホンディングパットを形成した
混成集積回路の側面図である。FIG. 3 is a side view of a hybrid integrated circuit in which bonding pads are formed on multilayer wiring.
第３図において、混成集積回路１はセラミック等からな
る絶縁基板２の上面に多層配線３を形成し、多層配線３
の上に複数個（図は９個）の外部接続用ホンティングバ
ッド４を形成してなる。In FIG. 3, a hybrid integrated circuit 1 has a multilayer wiring 3 formed on the upper surface of an insulating substrate 2 made of ceramic or the like.
A plurality of (nine in the figure) external connection honting pads 4 are formed on the board.
かかる混成集積回路１において、多層配線３内に形成し
ホンティングバンド４に接続する配線のチェック（断線
の有無）は、従来、ホンティングバンド４に試験用のプ
ローブを当接し実施していた。In such a hybrid integrated circuit 1, the wiring formed in the multilayer wiring 3 and connected to the honting band 4 has conventionally been checked (for the presence or absence of disconnection) by contacting the honting band 4 with a test probe.
以」二１悦明したように、プローブを使用し多層配線３
をチェックする従来方法は、例えば各ホンディングパッ
ド４に対向し複数本のプローブを植設した検出具を準備
し、該検出具に混成集積回路を搭載する。一般に、この
ようなプローブは適当な圧力でホンティングバンドに当
接させるため、圧縮コイルばねを内臓した構成であり、
特に多数のホンティングバンド４が近接し配設された多
層配線３のチェック用検出具は、プローブの作成が煩わ
しいと共に、各種の多層配線３にそれぞれ適用する専用
のものを必要とした。As mentioned above, multilayer wiring 3 using probes
In a conventional method for checking, for example, a detection tool is prepared in which a plurality of probes are implanted facing each bonding pad 4, and a hybrid integrated circuit is mounted on the detection tool. Generally, such probes have a built-in compression coil spring in order to bring them into contact with the honting band with appropriate pressure.
In particular, a detection tool for checking a multilayer wiring 3 in which a large number of honting bands 4 are disposed close to each other is troublesome to prepare a probe, and requires a dedicated device for each type of multilayer wiring 3.
即ち、多層配線をチェックする従来方法は、検出用プロ
ーブおよび多層配線に適用する検出具を作成する煩わし
さがあった。That is, in the conventional method of checking multilayer wiring, it is troublesome to prepare a detection probe and a detection tool to be applied to the multilayer wiring.
〔問題点を解決するための手段〕
」二記問題点の除去を目的とした本発明方法は、本発明
の実施例に係わる第１図によれば、絶縁基板１１の一方
の面に形成した多層配線１３の内部断線の有無を検査す
る方法であり、
多層配線１３の上面には多層配線１３内に形成し一連の
各配線にそれぞれ接続するパット２０を表呈せしめ、
絶縁基板１１には該一連の各配線かそれぞれ接続するス
ルーホール１２を形成し、
絶縁基板１１の他方の面にスルーホール１２と接続する
導体層２１を被着し、
導体層２１を電気めっき装置の陰極端子を接続して電解
めっき液２５に浸漬し、バッド２０に被着する電着層か
ら、多層配線１３の内部断線の有無を知ることを特徴と
する多層配線の検査方法である。[Means for Solving the Problems] According to FIG. This is a method of inspecting the presence or absence of internal disconnection in the multilayer wiring 13, in which pads 20 formed in the multilayer wiring 13 and connected to each series of wiring are exposed on the upper surface of the multilayer wiring 13, and pads 20 are formed on the insulating substrate 11 and connected to each series of wiring. Through-holes 12 are formed to connect each of the series of wires, a conductor layer 21 is deposited on the other side of the insulating substrate 11 to connect to the through-holes 12, and the conductor layer 21 is connected to the cathode terminal of an electroplating device. This is a multilayer wiring inspection method characterized by immersing the multilayer wiring 13 in an electrolytic plating solution 25 and determining whether or not there is an internal disconnection in the multilayer wiring 13 from the electrodeposited layer deposited on the pad 20.
上記手段によれば、電解めっきを多層配線の内部配線の
Ｕｒ線検知に利用することで、該検知が容易になると共
に、同一装置で各種多層配線のチェックに使用できるよ
うになる。さらに、ボンデイングバッドの形成工程と共
通化を可能にした。According to the above means, by using electrolytic plating to detect Ur wires in internal wiring of multilayer wiring, the detection becomes easy and the same device can be used to check various multilayer wiring. Furthermore, it has become possible to share the bonding pad formation process.
以下に、図面を用いて本発明方法の実施例を説明する。 Examples of the method of the present invention will be described below with reference to the drawings.
第１図は本発明方法の一実施例を説明するためその主要
工程を工程順に示ず側断面図、第２図は本発明方法で検
出した多層配線の不良部分を示す拡大断面図である。FIG. 1 is a side cross-sectional view of an embodiment of the method of the present invention without showing its main steps in order, and FIG. 2 is an enlarged cross-sectional view showing a defective portion of a multilayer wiring detected by the method of the present invention.
第１図（イ）において、絶縁基板１１の所定部にはスル
ーホール１２を形成する。In FIG. 1(A), a through hole 12 is formed in a predetermined portion of an insulating substrate 11. As shown in FIG.
第１図（１１）において、内部配線が各スルーホール１
２にそれぞれ接続する多層配線１３を絶縁基板１１の」
二面に形成する。多層配線１３は、絶縁基板１１の上面
に形成した複数の第１の導体パターン１４と、その上に
被着した絶縁層１５を貫通するピアホール１６に接続し
絶縁層１５の上に形成した複数の第２の導体パターン１
７と、その上に被着した絶縁層１８を貫通するピアホー
ル１９に接続するバッド２０にてなる。In Figure 1 (11), the internal wiring is connected to each through hole 1.
2, the multilayer wiring 13 connected to the insulating substrate 11, respectively.
Form on two sides. The multilayer wiring 13 includes a plurality of first conductor patterns 14 formed on the upper surface of the insulating substrate 11 and a plurality of first conductor patterns 14 formed on the insulating layer 15 connected to a peer hole 16 passing through the insulating layer 15 deposited thereon. Second conductor pattern 1
7 and a pad 20 connected to a pier hole 19 passing through an insulating layer 18 deposited thereon.
第１図（ハ）において、絶縁基板ＩＩの下面に例えばＴ
ａＮ層にＮｉＣｒ層、Ａｕ層を積層してなる薄膜導体層
２１を被着したのち、第１図（＝）に示すように、めっ
き電極と接続する部分を除いた薄膜導体層２１にレジス
ト層２２を被着する。In FIG. 1(c), for example, a T
After depositing a thin film conductor layer 21 formed by stacking a NiCr layer and an Au layer on the aN layer, as shown in FIG. 22 is applied.
次いで、第１図（＊）に示すように、薄膜導体層２１を
めっき電源２３の陰極側に接続し、めっき電源２３の陽
極（例えばＡｕにてなる陽極）２４と対向するように電
解めっき液２５に浸漬する。すると、多層配線１３の上
面に表呈し多層配線１３内で断線してないバッド２０に
は、Ａｕのポンディングパッド２６が形成される。しか
し、多層配線１３内で断線し薄膜導体層２１と接続しな
いバッド２０には、ホンディングバッド２６が形成され
ないことになる。Next, as shown in FIG. 1 (*), the thin film conductor layer 21 is connected to the cathode side of the plating power source 23, and an electrolytic plating solution is applied so as to face the anode (for example, an anode made of Au) 24 of the plating power source 23. 25. Then, Au bonding pads 26 are formed on the pads 20 that are exposed on the upper surface of the multilayer wiring 13 and are not disconnected within the multilayer wiring 13. However, no bonding pad 26 is formed on the pad 20 that is disconnected within the multilayer wiring 13 and is not connected to the thin film conductor layer 21 .
第２図において、右側のバッド２０は多層配線１３内の
導体層およびスルーホール１２を介し、薄膜導体層２１
と接続するためホンディングパッド２６が形成される反
面、左側のパッド２ｏは多層配線１３内の導体パターン
１７に断線があり薄膜導体層２１と接続しないたい、ポ
ンディングパッド２６が形成されない。In FIG. 2, the pad 20 on the right side is connected to the thin film conductor layer 20 through the conductor layer and through hole 12 in the multilayer wiring 13.
On the other hand, the pad 2o on the left side has a disconnection in the conductor pattern 17 in the multilayer wiring 13 and does not want to be connected to the thin film conductor layer 21, so no bonding pad 26 is formed.
従って、ホンディングパッド２６が形成または形成され
ないことで、各パッド２ｏに接続する多層配線１３内の
配線の断線の有無を検知できる。Therefore, by forming or not forming the bonding pad 26, it is possible to detect whether there is a disconnection in the wiring within the multilayer wiring 13 connected to each pad 2o.
なお、前記実施例において、多層配線１３の内部断線の
検出のため多層配線１３の表面に表呈せしめるパッドに
、ホンディングパッド２６を形成するためのパット２０
を利用している。しかし、ボンディング式ノド形成用パ
ッド２ｏのない混成集積回路では、多層配線Ｉ３の検査
用のパ・ノドを設ける必要がある。In the above embodiment, the pads 20 for forming the bonding pads 26 are provided on the pads exposed on the surface of the multilayer wiring 13 for detecting internal disconnections in the multilayer wiring 13.
is used. However, in a hybrid integrated circuit that does not have a pad 2o for forming a bonding type nozzle, it is necessary to provide a pad/node for inspecting the multilayer wiring I3.
また、前記実施例において、ＴａＮ、ＮｉＣｒ層、Ａｕ
層の積層構成になる薄膜導体層１８は、絶縁基板２の下
面に薄膜抵抗素子を形成させることに鑑みた構成であり
、かかる薄膜導体層１８を必要としない混成集積回路で
は、多層配線１３の検査用の導体層を絶縁基板１１の下
面に設ける必要かある。Further, in the above embodiments, TaN, NiCr layer, Au
The thin film conductor layer 18 having a laminated structure is designed in consideration of forming a thin film resistance element on the lower surface of the insulating substrate 2. In a hybrid integrated circuit that does not require such a thin film conductor layer 18, the multilayer wiring 13 is Is it necessary to provide a conductor layer for inspection on the lower surface of the insulating substrate 11?
以上説明したように本発明によれば、めっき手段を多層
配線内の断線検知に利用することで、従来方法で必要と
するプローブが不要となり、ホンディングパッドの配設
の異なる各種多層配線に共通装置で検知可能となり、か
つ、従来は２回に分ける必要があった高密度に配設した
ホンディングパッドを有する多層配線の内部の断線も１
回で検知可能とし、ポンディングパッドの形成を多層配
線の検査工程で実施可能である効果は極めて大きい。As explained above, according to the present invention, by using plating means to detect disconnections in multilayer wiring, the probe required in the conventional method is no longer required, and it is common to various multilayer wirings with different placement of bonding pads. The device can now detect internal disconnections in multilayer wiring with densely arranged bonding pads, which previously had to be separated into two.
The effect of being able to detect the bonding pad in one step and forming the bonding pad in the multilayer wiring inspection process is extremely large.
第１図は本発明方法の一実施例を説明するためその主要
工程を示す側断面図、
第２図は本発明方法で検出した多層配線の不良部分を示
す拡大断面図、
第３図は多層配線の上にホンディングパッドを形成した
混成集積回路の側面図、
である。
図中において、
１１は絶縁基板、
１２はスルーホール、
１３は多層配線、
２０はパッド、
２１は導体層、
２５は電解めっき液、
２７はホンディングパッド−１
を示す。
多屑低び彪の且にボ′〉デン〉り“′ｌマ、ンドＬツノ
、ｒ？” ＋ ｗ ＋９ −九Ｍ−Ｚ４ど）ｖｒ５
二 −Ｈ，−５１１乙ヒ９イの主留工程た示、１噸・［
断面閏
あ（図Fig. 1 is a side cross-sectional view showing the main steps for explaining one embodiment of the method of the present invention, Fig. 2 is an enlarged cross-sectional view showing a defective part of multilayer wiring detected by the method of the present invention, and Fig. 3 is a multilayer interconnection. 1 is a side view of a hybrid integrated circuit in which a bonding pad is formed on wiring. In the figure, 11 is an insulating substrate, 12 is a through hole, 13 is a multilayer wiring, 20 is a pad, 21 is a conductor layer, 25 is an electrolytic plating solution, and 27 is a bonding pad-1. Takuzu low and Biao's board'〉den〉"'lma, ndo Ltsuno, r?" + w +9 -9M-Z4 etc.)vr5
2 -H, -511 Demonstration of the main retention process of Otsuhi 9i, 1 story・[
Cross-section screw (Fig.
Claims (1)
３）の内部断線の有無を検査する方法であり、該多層配
線（１３）の上面には該多層配線（１３）内に形成し一
連の各配線にそれぞれ接続するパッド（２０）を表呈せ
しめ、 該絶縁基板（１１）には該一連の各配線がそれぞれ接続
するスルーホール（１２）を形成し、 該絶縁基板（１１）の他方の面に該スルーホール（１２
）と接続する導体層（２１）を被着し、 該導体層（２１）を電気めっき装置の陰極端子を接続し
て電解めっき液（２５）に浸漬し、該パッド（２０）に
被着する電着層から、該多層配線（１３）の内部断線の
有無を知ることを特徴とする多層配線の検査方法。[Claims] A multilayer wiring (1) formed on one surface of an insulating substrate (11).
3), in which pads (20) formed in the multilayer wiring (13) and connected to each series of wiring are exposed on the upper surface of the multilayer wiring (13). , through holes (12) are formed in the insulating substrate (11) to which the series of wirings are connected, and the through holes (12) are formed in the other surface of the insulating substrate (11).
), connect the conductive layer (21) to the cathode terminal of an electroplating device, immerse it in an electrolytic plating solution (25), and deposit it on the pad (20). A method for inspecting multilayer wiring, characterized in that the presence or absence of internal disconnection in the multilayer wiring (13) is determined from the electrodeposited layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3496787A JPS63202997A (en) | 1987-02-18 | 1987-02-18 | Inspection of multilayer interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3496787A JPS63202997A (en) | 1987-02-18 | 1987-02-18 | Inspection of multilayer interconnection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63202997A true JPS63202997A (en) | 1988-08-22 |
Family
ID=12428913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3496787A Pending JPS63202997A (en) | 1987-02-18 | 1987-02-18 | Inspection of multilayer interconnection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63202997A (en) |
-
1987
- 1987-02-18 JP JP3496787A patent/JPS63202997A/en active Pending
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