JPS6010798A - Method of mounting circuit element - Google Patents

Method of mounting circuit element

Info

Publication number
JPS6010798A
JPS6010798A JP11959083A JP11959083A JPS6010798A JP S6010798 A JPS6010798 A JP S6010798A JP 11959083 A JP11959083 A JP 11959083A JP 11959083 A JP11959083 A JP 11959083A JP S6010798 A JPS6010798 A JP S6010798A
Authority
JP
Japan
Prior art keywords
circuit
circuit board
circuit element
small
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11959083A
Other languages
Japanese (ja)
Inventor
中村 恒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11959083A priority Critical patent/JPS6010798A/en
Publication of JPS6010798A publication Critical patent/JPS6010798A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電子機器の回路基板に回路素子を取付ける回
路素子の取付は方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for mounting a circuit element on a circuit board of an electronic device.

従来例の構成とその問題点 −1− 近年、電子機器の小型軽♀化に対゛する要求が高まって
くるにつれ、電子機器を構成する回路素子の小型化やリ
ードレス化は急速に進んで来た。そして昨今では、これ
らの回路素子を回路基板に高密度に集積化するための技
術が重要な課題となっている。
Conventional configurations and their problems - 1 - In recent years, as the demand for smaller and lighter electronic devices has increased, circuit elements that make up electronic devices have rapidly become smaller and leadless. It's here. Recently, technology for integrating these circuit elements on a circuit board at high density has become an important issue.

従来、リードレス化された小型回路素子や、さらにはリ
ードを有する平面接続タイプの小型回路素子、例えばメ
タルグレーズ系のチップ抵抗器や積層セラミックから成
るチップコンデンサー、ミニモールド型のトランジスタ
、さらには半導体ICやLSIチップを超小型にパッケ
ージしたチップキャリアタイプの半導体装置などを微細
配線化した回路基板に高密度に取付ける場合の一般的な
方法としては、第1図A−Cに示す工程を経て行われる
。この方法は、まず第1図Aに示すように、ガラスエポ
キシなどの合成樹脂基板やアルミナなどのセラミックか
ら成る絶R基板1の表面に配線回路導体2を形成した回
路基板を用いて第1図Bに示すように、この回路基板の
配線回路導体2上−2− にクリーム状のはんだ3を塗布し、次いで第1図Cに示
すように、チップ抵抗器やチップコンデンサーなどの平
面接続タイプの小型回路素子4a、 4hをその接続端
子がクリーム状のはんだ3に接触するように回路基板上
にのせ、この回路基板を高温の熱炉を通してはんだ3を
再溶融させるいわゆるはんだリフロー法により、平面接
続タイプの小型回路素子4a、柿を回路基板に取イ1け
る方法である。
Conventionally, leadless small circuit elements and even planar connection type small circuit elements with leads, such as metal glaze chip resistors, multilayer ceramic chip capacitors, mini-molded transistors, and even semiconductors. The general method for mounting chip carrier-type semiconductor devices, etc., which are ultra-small packages of IC or LSI chips, on a circuit board with fine wiring is to go through the steps shown in Figure 1A-C. be exposed. In this method, first, as shown in FIG. 1A, a circuit board is used, in which wiring circuit conductors 2 are formed on the surface of an extremely rigid substrate 1 made of a synthetic resin substrate such as glass epoxy or a ceramic such as alumina. As shown in Fig. 1B, cream solder 3 is applied to the wiring circuit conductor 2 of this circuit board -2-, and then, as shown in Fig. The small circuit elements 4a and 4h are placed on a circuit board so that their connection terminals are in contact with the creamy solder 3, and the circuit board is passed through a high-temperature furnace to remelt the solder 3, which is the so-called solder reflow method, to make a planar connection. This is a method of attaching a type of small circuit element 4a and a persimmon to a circuit board.

ところが、このような従来の回路素子の取付は方法では
、次のような不都合な問題があった。
However, this conventional circuit element mounting method has the following disadvantages.

■ はIυだリフロ一時に、小型回路素子4a、 4b
の位置ズレが発生しゃすいたが)、高集積化した回路構
成が困丼である。
■ is Iυ At the time of reflow, small circuit elements 4a and 4b
However, the highly integrated circuit structure is difficult.

■ はんだリフロ一時に、はんだクリームに含まれてい
るフラックスと共にはんだ3の飛沫が飛散し、配線回路
導体2間の短絡不良が発生しやすい。
■ During solder reflow, droplets of the solder 3 are scattered together with the flux contained in the solder cream, and a short circuit between the wiring circuit conductors 2 is likely to occur.

■ 小型回路素子4a、 4hを密集させたり、例えば
半導体ICの小型パッケージ等のように端子ピッチが狭
いものを取付レノる場合には、は−3− んだのブリッジや接続不良が発生しヤ)すく、その修正
が煩雑である。
■ When small circuit elements 4a and 4h are packed together or when mounting items with narrow terminal pitches, such as small packages for semiconductor ICs, solder bridges and poor connections may occur. ), the correction is complicated.

■ はんだリフr〕一時に高温にさらされるため、小型
回路素子4a、 4b亡回路基板の耐熱性が制約される
[Solder ref] Since the small circuit elements 4a and 4b are exposed to high temperatures at one time, the heat resistance of the circuit board is restricted.

発明の目的 本発明は上記従来の欠点を解消するもので、電子機器の
組立てに際し、より高集積化した電子回路基板を構成す
ることのできる回路素子の取付は方法を提供することを
目的とする。
OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional drawbacks, and an object of the present invention is to provide a method for mounting circuit elements that can configure a more highly integrated electronic circuit board when assembling electronic equipment. .

発明の構成 −h記目的を達成するため、本発明の回路素子の取付は
方法は、絶縁基板の少なくとも一方の主面に配線回路状
の導体層を形成した回路基板に接着剤を用いて平面接続
タイプの回路素子を固定し、無電解めっきにより導電金
属層を形成して前記回路基板と回路素子とを電気的に接
続する/J法l・、:。
Structure of the Invention In order to achieve the object (h), the method for mounting a circuit element of the present invention is to mount a circuit element on a flat surface using an adhesive on a circuit board on which a conductive layer in the form of a wiring circuit is formed on at least one main surface of an insulating board. A connection type circuit element is fixed, and a conductive metal layer is formed by electroless plating to electrically connect the circuit board and the circuit element.

る。Ru.

実施例の説明 ] 以下、本発明の一実施例について、図面に基づ−4− いて説明する。Description of Examples] Hereinafter, one embodiment of the present invention will be described based on the drawings. I will explain.

第2図A−Dは平面接続タイプの小型回路素子の取付は
方法を説明するための各工程における回路基板の要部断
面図である。第2図において、5は絶縁基板、6は絶縁
基板5上に形成された配線回路状の導体層、7は導体層
6.6間に塗布された接着剤、8a、 8bは平面接続
タイプの小型回路素子、9は無電解めっきにより析出し
た導電金属層である。
FIGS. 2A to 2D are sectional views of essential parts of the circuit board at each step for explaining the mounting method of a flat connection type small circuit element. In Fig. 2, 5 is an insulating substrate, 6 is a wiring circuit-shaped conductor layer formed on the insulating substrate 5, 7 is an adhesive applied between the conductor layers 6 and 6, and 8a and 8b are planar connection type. The small circuit element 9 is a conductive metal layer deposited by electroless plating.

回路素子の取付けに際しては、まず第2図へに示すよう
に、ガラスエポキシ積層板などの合成樹脂基板から成る
絶縁基板5の主面に銅はくから成る配線回路状の導体層
6を形成した回路基板を用いて、第2図Bに示すように
、回路基板の導体層6.6間にエポキシ樹脂やアクリル
樹脂などの熱硬化性樹脂から成る接着剤7をスクリーン
印刷法やディスペンサーを用いて所定量を塗布し、次い
で第2図Cに示すように、この接着剤7の上に、電気回
路を構成するのに必要な平面接続タイプの小型回路素子
8a、 8bとして、例えばメタルグレー−5− ズ系のチップ抵抗器や、積居セラミック型のチップコン
デンサー、リードレスタイプのタンタル固体電解コンデ
ンサー、積層型のチップインダクター、さらには半導体
ICやLSIチップの超小型の樹脂モールドパッケージ
などを載せ、加圧して各小型回路素子8a、 8bの外
部接続端子と回路基板のη体層6とを精度良く接触させ
てから、接着剤7を加熱硬化した後で、この回路基板を
銅やニッケルなどの無電解めっぎ液に浸漬して、第2図
りに示すように回路基板の導体層6及び小型回路素子8
a、 8bの外部接続端子に銅やニッケルなどの導電金
R層9を析出させ、小型回路素子8a 、 8bと回路
基板の導体層6との電気的接続を行う。
When installing the circuit elements, first, as shown in FIG. 2, a wiring circuit-shaped conductor layer 6 made of copper foil is formed on the main surface of an insulating substrate 5 made of a synthetic resin substrate such as a glass epoxy laminate. Using a circuit board, as shown in Figure 2B, an adhesive 7 made of a thermosetting resin such as epoxy resin or acrylic resin is applied between the conductor layers 6.6 of the circuit board using a screen printing method or a dispenser. A predetermined amount of adhesive is applied, and then, as shown in FIG. - Equipped with multi-layer chip resistors, multilayer ceramic chip capacitors, leadless tantalum solid electrolytic capacitors, multilayer chip inductors, and ultra-small resin molded packages for semiconductor ICs and LSI chips. After pressurizing the external connection terminals of each small circuit element 8a, 8b and bringing them into precise contact with the η body layer 6 of the circuit board, and curing the adhesive 7 by heating, the circuit board is bonded with copper, nickel, etc. The conductor layer 6 and small circuit elements 8 of the circuit board are immersed in an electroless plating solution as shown in the second diagram.
A conductive gold R layer 9 made of copper or nickel is deposited on the external connection terminals 8a and 8b to electrically connect the small circuit elements 8a and 8b to the conductor layer 6 of the circuit board.

第3図は第2の実施例を説明するための回路基板の要部
断面図で、この実施例は、平面接続タイプの小型回路素
子8a、 8bを回路基板に固定するのに、回路基板の
導体層6に銅や銀の微粉末をエポキシ樹脂などの熱硬化
性樹脂に分散したいわゆる導電性の接着剤10を塗布し
て、小型回路素子8a。
FIG. 3 is a cross-sectional view of a main part of a circuit board for explaining the second embodiment. A so-called conductive adhesive 10 in which fine powder of copper or silver is dispersed in a thermosetting resin such as an epoxy resin is applied to the conductor layer 6 to form a small circuit element 8a.

8bを固定し、無電解めっきにより、S電性の接着−6
− 剤10の表面に導電金属層9を析出したものである。
8b is fixed and electroless plating is used to create S-electrode adhesion-6.
- A conductive metal layer 9 is deposited on the surface of the agent 10.

この実施例は、小型回路素子8a、 8hが導電性の接
着剤10によってあらかじめ回路基板の導体層6と電気
的に接続された状態で無電解めつぎを行って、より確実
な電気的接続が(■られるようにし1cこ(にを特徴と
する。
In this embodiment, electroless bonding is performed with the small circuit elements 8a and 8h electrically connected in advance to the conductor layer 6 of the circuit board using a conductive adhesive 10, thereby achieving a more reliable electrical connection. (Characterized by 1c).

なお、」−記実施例においては、小型回路素子Ra。In addition, in the embodiment shown in "-", the small circuit element Ra.

8bを取付(づるための回路基板どして、ガラス王ボキ
シ積層板などの合成樹脂製の絶縁基板5上に銅はくから
成る導体層6を形成した例について説明したが、本発明
はこのJ:う′/、に構成に限定されろものではなく、
アルミナなどのセラミックス’Flの絶縁基板5上に銀
や銅、さらにはタングステン、モリブデンなどから成る
いわゆる厚膜ペーストを用いて高温焼成4ろことにより
導体層6を形成したものや、ポリイミド、ポリエステル
なとのフィルム状の絶縁基板5に銅はくから成るう9体
層6を形成したものなど、使用目的に応じいろいろなf
I類のものを用い1′:Iろことは勿論である。
An example has been described in which a conductor layer 6 made of copper foil is formed on an insulating substrate 5 made of a synthetic resin such as a glass boxy laminate as a circuit board for attaching the 8b. J: U'/, it is not limited to the composition,
A conductor layer 6 is formed on an insulating substrate 5 made of ceramics such as alumina by high-temperature firing using a so-called thick film paste made of silver, copper, tungsten, molybdenum, etc., or a conductive layer 6 made of polyimide, polyester, etc. There are various types of F according to the purpose of use, such as one in which nine layers 6 made of copper foil are formed on a film-like insulating substrate 5.
Of course, a 1':I filter is used.

また、小型回路素子8a、 Rhは、無電解めっき液−
7− 中に浸漬されるため、無電解めつぎ液によって特性劣下
を起こさない構造のものを使用することが必要不可欠で
あるが、通常のセラミックをベースとしたリードレスデ
ツプ抵抗器やブツプコンデンサーは充分に使用に耐える
ことを確認した。しかし、半導体ICやLSIでは、そ
れらのチップが確実に樹脂用11−かハーメチックシー
ルされたちのを使用しないと、特性不良を起こすことが
確認された。
Moreover, the small circuit element 8a, Rh is coated with an electroless plating solution.
7- Since the capacitor is immersed in the electroless potting solution, it is essential to use a capacitor with a structure that does not deteriorate its characteristics due to the electroless potting solution, but ordinary ceramic-based leadless dip resistors and bump capacitors are It was confirmed that it was sufficiently durable for use. However, in semiconductor ICs and LSIs, it has been confirmed that if the chips are not made of resin or hermetically sealed chips, they will have poor characteristics.

発明の詳細 な説明したように本発明によれば、従来のはんだリフロ
ー法による取付は方法に比べて、次のような効果が得ら
れる。
DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the following effects can be obtained compared to the conventional solder reflow method.

■ 無電解めっきによって、平面接続タイプの回路素子
を回路基板に電気的に接続するので、回路素子を密集し
て回路基板に取付けても、その電気的な接続を確実に行
え、高集積化した回路基板を得ることができる。
■ Since planar connection type circuit elements are electrically connected to the circuit board using electroless plating, even if the circuit elements are mounted closely together on the circuit board, the electrical connection can be made reliably, making it possible to achieve high integration. A circuit board can be obtained.

■ 回路素子の接続に際して、はんだリフロー法のよう
な高温を必要としないので、回路素−8− 了や回路基板の湿度的な制約がなく、44 )’it選
択の自由面が広くなる。
(4) Since high temperatures as in the solder reflow method are not required when connecting circuit elements, there are no restrictions regarding the temperature of the circuit elements or the humidity of the circuit board, providing greater freedom of choice.

■ 外部接続端子のピッチが極めて小さい回路素子、特
に半導体ICや[STチップを超小型にパッケージした
ものを、微細5線化した回路基板」−に多数個取付ける
場合でも、’3i、ffl子間の短絡が全くなく、確実
に電気的接続ができ、接続の信頼性もはんだ接続したも
のに比べて極めて良好である。
■ Even when installing a large number of circuit elements with extremely small pitches of external connection terminals, especially semiconductor ICs or [circuit boards made of ultra-compact ST chips packaged into five wires] There is no short circuit at all, a reliable electrical connection is possible, and the reliability of the connection is also extremely good compared to those connected by soldering.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図Δ〜Cは(K東方法の主要T程における回路基板
の要部断面図、第2図A〜Dは本発明の第1の実施例に
おt−Jろ回路素子の取付方法の1−要工程における回
路基板の要部断面図、第3図は本発明の第2の実施例に
おける回路素子の取イく1方法により回路素子を取付け
た回路基板の要部断面図であるわ 5・・・IP!縁基板基板・・・導体層、7,10・・
・接着剤、8a、 8b・・・小型回路素子〈回路素子
)、9・・・導電金属層 −9− 第I図 (A) CB>
Figures 1 Δ to C are cross-sectional views of the main parts of the circuit board at the main T section of the K East method, and Figures 2 A to D are the method for mounting circuit elements in the first embodiment of the present invention. Fig. 3 is a cross-sectional view of a main part of a circuit board in which a circuit element is attached by one method of removing a circuit element in a second embodiment of the present invention. 5...IP! Edge board board...conductor layer, 7, 10...
・Adhesive, 8a, 8b... Small circuit element (circuit element), 9... Conductive metal layer -9- Figure I (A) CB>

Claims (1)

【特許請求の範囲】 1、絶縁基板の少なくとも一方の主面に配線回路状の導
体層を給酸した回路基板に接着剤を用いて平面接続タイ
プの回路素子を固定し、無電解めっきにより導電金属層
を形成して前記回路基板と回路素子とを電気的に接続す
る回路素子の取付は方法。 2、回路素子を回路基板に固定するに際し、回路基板の
導体層に導電性の接着剤を塗布し、この導電性の接着剤
により前記回路素子の外部接続端子を固定する構成とし
た特許請求の範囲第1項記載の回路素子の取付は方法。
[Claims] 1. A planar connection type circuit element is fixed using an adhesive to a circuit board which has a conductor layer in the form of a wiring circuit on at least one main surface of an insulating substrate, and is conductive by electroless plating. A method for mounting a circuit element in which a metal layer is formed to electrically connect the circuit board and the circuit element. 2. When fixing the circuit element to the circuit board, a conductive adhesive is applied to the conductive layer of the circuit board, and the external connection terminals of the circuit element are fixed with the conductive adhesive. The method for installing the circuit elements described in Scope 1.
JP11959083A 1983-06-30 1983-06-30 Method of mounting circuit element Pending JPS6010798A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11959083A JPS6010798A (en) 1983-06-30 1983-06-30 Method of mounting circuit element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11959083A JPS6010798A (en) 1983-06-30 1983-06-30 Method of mounting circuit element

Publications (1)

Publication Number Publication Date
JPS6010798A true JPS6010798A (en) 1985-01-19

Family

ID=14765135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11959083A Pending JPS6010798A (en) 1983-06-30 1983-06-30 Method of mounting circuit element

Country Status (1)

Country Link
JP (1) JPS6010798A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014086246A (en) * 2012-10-23 2014-05-12 Nippon Mektron Ltd Flexible printed wiring board with bus bar, and method of manufacturing the same, and battery system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55145393A (en) * 1979-04-30 1980-11-12 Matsushita Electric Works Ltd Method of mounting electronic component

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55145393A (en) * 1979-04-30 1980-11-12 Matsushita Electric Works Ltd Method of mounting electronic component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014086246A (en) * 2012-10-23 2014-05-12 Nippon Mektron Ltd Flexible printed wiring board with bus bar, and method of manufacturing the same, and battery system
US10084211B2 (en) 2012-10-23 2018-09-25 Nippon Mektron, Ltd. Flexible printed circuit with bus bars, manufacturing method thereof, and battery system

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