JPS6010657A - Manufacture of resistor - Google Patents
Manufacture of resistorInfo
- Publication number
- JPS6010657A JPS6010657A JP11961283A JP11961283A JPS6010657A JP S6010657 A JPS6010657 A JP S6010657A JP 11961283 A JP11961283 A JP 11961283A JP 11961283 A JP11961283 A JP 11961283A JP S6010657 A JPS6010657 A JP S6010657A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- resistance values
- impurity
- resistors
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 230000001788 irregular Effects 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000002131 composite material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、特に多結晶シリコン層に不純物なドーピン
グして抵抗体ｌ形成する抵抗体の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a method of manufacturing a resistor in which a polycrystalline silicon layer is doped with impurities to form a resistor.
最近、組立コストの低減および信頼性の向上を目的とし
て、単体のトランジスタ、ダイオードあるいは抵抗等で
形成されていた回路部分！モノリシック化した複合素子
が発表されている。この複・合素子の１つとして、トラ
ンジスタと抵抗ヶモノリシックに組み−込んだ素子ｃ以
下抵抗材きＴＲと称テ）゛が発表されているーこのよう
な抵抗付きＴＲにおいては、抵抗体の抵抗値のバラツキ
が大きくて、従来の単体トランジスタと抵抗体で組んだ
回路より精度が悪くなわば、このような抵抗付きＴＲの
メリットはなくなる。したがって、抵抗付きＴＲにおい
ては、抵抗値のバラツキは小さく押さえなければならな
い。抵抗体でいえば、現在のモノリシック集積回路装置
の抵抗値のバラツキは±３０％程度であるが、抵抗付き
ＴＲでは±１０％程度の精度が要求されている。Recently, with the aim of reducing assembly costs and improving reliability, circuit parts that were formed from single transistors, diodes, or resistors! Monolithic composite devices have been announced. As one of these composite elements, a transistor and a resistor are monolithically incorporated into an element (hereinafter referred to as a "TR") with a resistor material below. In such a TR with a resistor, the resistance value of the resistor is If the variation in resistance is large and the accuracy becomes worse than a conventional circuit made up of a single transistor and a resistor, the merits of such a TR with a resistor disappear. Therefore, in a TR with a resistor, the variation in resistance value must be kept small. In terms of resistors, current monolithic integrated circuit devices have variations in resistance values of about ±30%, but TRs with resistors are required to have an accuracy of about ±10%.
さらに、このような抵抗付きＴＲにおいて、抵抗値のバ
ラツキが小さく、かつ、抵抗値が大きく異なる２個の抵
抗体を形成したい場合はモノリシック化するのはさらに
難しく、従来は単体の抵抗体とトランジスタな使って回
路ン形成していた。Furthermore, in such a TR with a resistor, if you want to form two resistors with small variations in resistance value and greatly different resistance values, it is even more difficult to make it monolithic. It was used to form circuits.
この発明は、上記の点忙かんがみなされたもので、抵抗
値が大きく異なり、かつ、それぞれの抵抗値のバラツキ
が小さい２個の抵抗体な持つ抵抗付きＴＲの抵抗体の製
造方法を提供するものである。以下この発明の一実施例
を第１図（ａ）〜（ｅ）に基づいて詳細に説明する。The present invention has been made in view of the above-mentioned problems, and provides a method for manufacturing a resistor-equipped TR having two resistors with greatly different resistance values and small variations in their resistance values. It is. Hereinafter, one embodiment of the present invention will be described in detail based on FIGS. 1(a) to (e).
まず、第１図（ａ）Ｖｃ示すように、通常の製造方法に
よって、半導体基板１にベース領域２１形成した後、ベ
ース領域２内にエミッタ領域３を形成する。その後、半
導体基板１の一生面上忙絶縁膜４を介して多結晶シリコ
ン膜５を、２０００’Ａ程度の厚さに被着する。続いて
、第１図（ｂ）に示すように、後忙第１．第２の抵抗体
６および７となる多結晶シリコン層を所定の部分忙形成
する。次に、第１図（ｃ） Ｋ示すように、低抵抗とな
る方の第１の抵抗体６以外をレジスト膜８で第２の抵抗
体７を含む半導体基板１の一生面上を覆った後、第１の
抵抗体６Ｖｃイオン注入で不純物なドープする。次如、
レジスト膜８１除去した後、第１の抵抗体６を含む半導
体基板１に、所定の温度Ｔ１で熱処理１行う。First, as shown in FIG. 1(a) Vc, a base region 21 is formed in a semiconductor substrate 1 by a normal manufacturing method, and then an emitter region 3 is formed in the base region 2. Thereafter, a polycrystalline silicon film 5 is deposited on the entire surface of the semiconductor substrate 1 via the insulating film 4 to a thickness of about 2000'A. Subsequently, as shown in FIG. 1(b), the busy schedule 1. A polycrystalline silicon layer which will become second resistors 6 and 7 is formed in predetermined portions. Next, as shown in FIG. 1(c) K, the entire surface of the semiconductor substrate 1 including the second resistor 7 was covered with a resist film 8 except for the first resistor 6 which had a lower resistance. After that, the first resistor is doped with impurities by 6Vc ion implantation. Next,
After removing the resist film 81, the semiconductor substrate 1 including the first resistor 6 is subjected to heat treatment 1 at a predetermined temperature T1.
次に、第１図（ｄ）Ｋ示すように、高抵抗となる方の第
２の抵抗体７以外ｌ第１の抵抗体６を含む半導体基板１
の一生面をレジスト膜８′で覆った後、第２の抵抗体７
Ｖｃイオン注入で所定の量の不純物ｌドープする。その
後レジスト膜８′夕除去し、第１の抵抗体６に加えた熱
処理温度Ｔ、より低温度Ｔ２で半導体基板ＩＫ熱処理を
行う。続いて、第１図（ｅ）に示すように、ベース領域
２．エミッタ領域３に電極コンタクト用の窓な開けた後
、それぞれベース！ｆｆ１９．エミッタ電極１０．コレ
クタ電極１１．および抵抗取出し電極１２を被着し、目
的とする抵抗付きＴＲを得ることができる。Next, as shown in FIG. 1(d)K, the semiconductor substrate 1 includes the first resistor 6 other than the second resistor 7 which has a high resistance.
After covering the entire surface of the resistor 7 with a resist film 8', the second resistor 7 is
A predetermined amount of impurity L is doped by Vc ion implantation. Thereafter, the resist film 8' is removed, and the semiconductor substrate is subjected to IK heat treatment at a heat treatment temperature T applied to the first resistor 6, but at a lower temperature T2. Subsequently, as shown in FIG. 1(e), the base region 2. After opening a window for electrode contact in emitter region 3, each base! ff19. Emitter electrode 10. Collector electrode 11. Then, a resistor lead-out electrode 12 is applied to obtain the desired resistor-equipped TR.
ここで、第２図は同じ寸法の多結晶シリコン層９４゜
中に同じ量の不純物をイオン注入で、ドープ量３ｘ １
０” ａｔｏｍｓ／ａｍ”をドープした抵抗体の不純物
）ｊ−７’後の熱処理温度依存性な示したものであるが
、同じ形状で同量の不純物なドープした試料でも熱処理
温度の違いによって大きな抵抗値の差が、ゆアい、。
１
また、第３図は２つの抵抗体に不純物を、ドープ量３
Ｘ １０”ａｔｏｍｓ／ｃｍ” Ｃ曲ｍＴ）とＩ Ｘ
１０”ａｔｏｍｓ／Ｃｍ２（曲線ＩＩ） ”ｋドープし
た後、第１回目〜第４回目まで、順次１１００’Ｃ，，
１０００’Ｃ。Here, in FIG. 2, the same amount of impurity is ion-implanted into a polycrystalline silicon layer 94° with the same dimensions, and the doping amount is 3x1.
The dependence of the impurities on the resistor doped with 0" atoms/am) on the heat treatment temperature after J-7' is shown, but even for samples doped with the same amount of impurities in the same shape, there is a large difference in the heat treatment temperature. The difference in resistance is huge.
1 In addition, Figure 3 shows that two resistors are doped with impurities, and the doping amount is 3.
X 10”atoms/cm” C song mT) and I
10"atoms/Cm2 (Curve II) "After doping, 1100'C,...
1000'C.
８００℃、１１００℃で熱処理したものである。Heat treated at 800°C and 1100°C.
このように高温度で熱処理した後、同一試料なこの高温
度より低い温度で熱処理した場合はほとんど抵抗値の変
化は見られない。なお、横軸は熱処理回数、縦軸は抵抗
値な示す。When the same sample is heat-treated at such a high temperature and then heat-treated at a temperature lower than this high temperature, almost no change in resistance value is observed. Note that the horizontal axis shows the number of heat treatments, and the vertical axis shows the resistance value.
この発明は、これらの実験結果から得られたものであり
、この発明による抵抗付きＴＲにおいては、第１の抵抗
体６および第２の抵抗体７の不純物ドープ後、異なった
温度で熱処理されているために大幅に抵抗値が異なって
おり、かつ、不純物ドープ量の精度の良好なイオン注入
で不純物のドープを行っているために、抵抗値は目標値
忙精度よくコントロールすることができるとともに、バ
ラツキも小さく押さえることができ、所望の抵抗付きＴ
Ｒ’＆得ることができる。The present invention was obtained from these experimental results, and in the resistor-equipped TR according to the present invention, after the first resistor 6 and the second resistor 7 are doped with impurities, they are heat-treated at different temperatures. Since the impurity is doped by ion implantation with high precision in the amount of impurity doped, the resistance value can be precisely controlled to the target value. Variations can be kept small and T with the desired resistance can be achieved.
R'& can be obtained.
２個の第１．第２の抵抗体６．７の抵抗値の差は、多結
晶シリコンへの不純物ドープ量な変えることにより、さ
らに大きくすることができるのはもちろんである。Two first. Of course, the difference in resistance value of the second resistor 6.7 can be further increased by changing the amount of impurity doped into the polycrystalline silicon.
以上説明したように、この発明によれば、抵抗値の大き
く異なった、かつ、抵抗値のバラツキの小さい抵抗体な
同一半導体基板上に形成することができるため、回路の
部品点数ｌ減らし、かつ、組立コストの低減２回路の信
頼性の向上に大きな効果を得ることができる。As explained above, according to the present invention, resistors having widely different resistance values and small variations in resistance values can be formed on the same semiconductor substrate, thereby reducing the number of circuit parts and , it is possible to obtain significant effects in reducing assembly costs and improving reliability of the two circuits.
第１図（ａ）〜ｒｅ）はこの発明の一実施例１示す抵抗
体の製造方法な示す工程別断面図、第２図は多結晶シリ
コン層中忙同じ量の不純物ｌイオン注入でドープした抵
抗体の不純物ドープ後の熱処理温度依存性を示す図、第
３図は不純物イオン注入後同一試料に熱処理ｌ、異なっ
た温度（高温から低温へ）で繰り返し加えたときの抵抗
値の変化ｌ示す相関図である。
図中、１はシリコン基板、４は絶縁膜、６． ７は第１
．第２の抵抗体である。なお、図中の同゛−符号は同一
または相当部分な示す。
第１図
第１図
−彰―麺 ｑ
−穎塀＠ＳFigures 1 (a) to (re) are cross-sectional views showing step-by-step cross-sectional views of a method of manufacturing a resistor according to Embodiment 1 of the present invention, and Figure 2 is a polycrystalline silicon layer doped with the same amount of impurity l ion implantation. Figure 3 shows the temperature dependence of heat treatment after impurity doping in a resistor. Figure 3 shows the change in resistance when heat treatment is repeatedly applied to the same sample at different temperatures (from high temperature to low temperature) after impurity ion implantation. It is a correlation diagram. In the figure, 1 is a silicon substrate, 4 is an insulating film, and 6. 7 is the first
．． This is the second resistor. Note that the same reference numerals in the figures indicate the same or corresponding parts. Fig. 1 Fig. 1 - Akira - Noodles q - Yingbei @S
Claims (1)
少なくとも第１と第２の抵抗体を形成する製造方法にお
いて、前記第１の抵抗体となる多結晶シリコン層に不純
物をドープした後所定の温度で熱処理を行い前記第１の
抵抗体を形成する工程、次に第２の抵抗体となる多結晶
シリコン層に不純物をドープした後、前記第１の抵抗体
の作成時の熱処理温度より低い温度で熱処理を行い前記
第２の抵抗体な形成する工程を含むことｔ特徴とする抵
抗体の製造方法。In a manufacturing method in which at least first and second resistors are formed by doping a polycrystalline silicon layer on a semiconductor substrate with an impurity, after doping the polycrystalline silicon layer that will become the first resistor with an impurity, A step of performing heat treatment at a temperature to form the first resistor, then doping an impurity into the polycrystalline silicon layer that will become the second resistor, and then performing a heat treatment at a temperature lower than that at which the first resistor was created. A method for manufacturing a resistor, comprising the step of performing heat treatment at a high temperature to form the second resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11961283A JPS6010657A (en) | 1983-06-29 | 1983-06-29 | Manufacture of resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11961283A JPS6010657A (en) | 1983-06-29 | 1983-06-29 | Manufacture of resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6010657A true JPS6010657A (en) | 1985-01-19 |
Family
ID=14765722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11961283A Pending JPS6010657A (en) | 1983-06-29 | 1983-06-29 | Manufacture of resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010657A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107919346A (en) * | 2016-10-10 | 2018-04-17 | 北大方正集团有限公司 | The production method of polysilicon resistance |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50134782A (en) * | 1974-04-15 | 1975-10-25 |
-
1983
- 1983-06-29 JP JP11961283A patent/JPS6010657A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50134782A (en) * | 1974-04-15 | 1975-10-25 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107919346A (en) * | 2016-10-10 | 2018-04-17 | 北大方正集团有限公司 | The production method of polysilicon resistance |
| CN107919346B (en) * | 2016-10-10 | 2019-12-31 | 北大方正集团有限公司 | Method for manufacturing polysilicon resistor |
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