JPH01128521A - Ion implantation - Google Patents

Abstract

PURPOSE:To precisely and easily control the depth of an outside layer without misregistration of the outside layer and the inside layer by ion-implanting impurities giving prescribed electrically conductive form on the surface of a semiconductor through a second ion implantation in which a second impurity ion is implanted in shallower and higher peak concentration than a first ion implantation. CONSTITUTION:A mask 5 attached to the surface of a semiconductor is commonly used in a first ion-implantation process and a second ion-implantation process, and both the ion-implantation process is continuously performed without inserting heat treatment and the like between the first ion-implantation process and the second ion-implantation process. This peak concentration Np2 is higher than that Np1 of the first ion-implantation process, for example, ion-implantation is X10<21>atom/cm<3> and ion-implantation depth X2 is shallower than the first ion-implantation depth X1, for example, 0.13mum. Therefore, misregistration of an outside layer 12 and an inside layer 22 is not produced. Further, since the depth of the outside layer 12 is determined in a heat treatment process, the depth of the outside layer 12 can be controlled precisely.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an ion implantation method suitable for forming a semiconductor layer in a semiconductor for field effect transistors, bipolar transistors, etc. The present invention relates to a method of ion-implanting impurities that provide .

[Conventional technology]

One of the basic performances of the above-mentioned field effect transistors and bipolar transistors is the withstand voltage value of these transistors, and in order to improve this performance and expand the range of applications of transistors, it is important to improve the semiconductor layer that makes up these transistors. For example, the source and drain of a field effect transistor or the base layer of a bipolar transistor are two-layered semiconductor layers, both of which have the same conductivity type, but the outer layer has a relatively low impurity concentration and is deep. It is advantageous to have a relatively large semiconductor layer, the inner layer of which has a higher impurity concentration and smaller depth than the outer layer. In such a two-layer semiconductor layer, the outer layer with a lower impurity concentration bears a higher voltage due to the junction between it and the semiconductor substrate, and the inner layer with a higher impurity concentration carries the two-layer semiconductor layer. It serves to reduce the voltage drop caused by the flowing current or between it and the electrode film.

Of course, such a two-layer semiconductor layer is also useful for high voltage diodes. As is well known, FIG. 6 shows a conventional method of forming such a two-layered semiconductor layer into a semiconductor using ion implantation.

In FIG. 6+a), the semiconductor substrate 31 or epitaxial layer is, for example, n-type as shown in the figure, and has an oxide film 32 deposited on its surface, and a photoresist or mask film 33 coated thereon. The oxide film 32 in that part is removed by etching using the window 33a, and B ions are implanted as a p-type impurity through this window by ion implantation to remove the implanted p-type impurity 34a.
After removing the mask 33, the p-type outer layer 34 is re-diffused to a predetermined depth by thermal diffusion under high temperature, and a p-type outer layer 34 is first formed in the substrate 31, as shown in FIGS. Same figure (
C) is the second ion implantation step, in which the mask film 35
is again applied on the oxide film 32, a window 35a which is slightly narrower than the previous window 33a is opened, the oxide film 32 underneath is removed by etching, and ions of, for example, B are again implanted through this window 35a by ion implantation. The impurity 36a implanted in this way is implanted at a higher concentration than the previous time.
As before, it is re-diffused by high temperature thermal diffusion upon removal of the mask 35, thereby creating a strong p-type inner layer 36 inside the outer layer 34, as shown in the figure (dl).
During the second thermal diffusion, the depth of the outer layer 34 is slightly larger than that of the previous time. A semiconductor with a two-layer structure consisting of an outer layer 34 having a predetermined depth of 0 or more, and an inner layer 36 shallower than that but having a high impurity concentration. A layer is built into a semiconductor substrate 1 .

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, two ion implantation steps and two thermal diffusion steps or a so-called drive-in step are required in order to create a double-structured semiconductor layer in a semiconductor.
Naturally, this requires twice as much effort as when manufacturing a semiconductor layer with a single configuration. In addition, it is necessary to attach a mask to the semiconductor surface for each ion implantation process, which takes time and effort for the photo process, and requires careful mask alignment during the second photo process, which may result in insufficient mask alignment accuracy. If there is, as shown in FIG.
If it protrudes beyond the range of , the function as a double semiconductor layer is lost, resulting in breakdown voltage failure. Furthermore, since the outer layer 34 is re-diffused during each of the two drive-in steps, its depth tends to vary due to variations in the two-time diffusion conditions, making it difficult to manage the breakdown voltage value.

The present invention solves these problems and creates a semiconductor layer with a double structure consisting of a deep outer layer with a relatively low impurity concentration and a shallow inner layer of the same conductivity type but with a high impurity concentration, using fewer steps than before. The object of the present invention is to provide an ion implantation method that can be incorporated into a semiconductor, eliminates the problem of positional misalignment between the outer layer and the inner layer, and particularly facilitates precise control of the depth of the outer layer.

[Means for solving problems]

In order to create the above-mentioned double-structured semiconductor layer in a semiconductor, the present invention provides a mask film that is applied to the surface of the semiconductor, and then a window is opened at the location where impurity ions are to be implanted, and the mask is used as a mask for ion implantation. a first ion implantation step of implanting first impurity ions to a predetermined depth and peak concentration using the mask to impart a predetermined conductivity type to the semiconductor; and a first ion implantation step. A second ion implantation process uses the same mask to implant second impurity ions that give the semiconductor the same conductivity type as the first impurity ions, at a shallower depth (and a higher peak concentration) than in the first ion implantation step. By ion-implanting an impurity that imparts a predetermined conductivity type to the surface of the semiconductor through steps including the above steps, the above object or problem was successfully achieved.

[Effect]

As can be seen from the above structure, the present invention uses a mask attached on the surface of the semiconductor in the mask forming process in common in the first ion implantation process and the second ion implantation process, and Either of the first ion implantation step and the second ion implantation step for the inner layer may be performed first, but heat treatment etc. may be performed between the first ion implantation step and the second ion implantation step. Both ion implantation steps are performed consecutively without inserting any additional steps. According to this configuration of the present invention, since a mask is used in common for both ion implantation steps, only one photo process is required, and misalignment between the outer layer and the inner layer cannot occur.

In addition, since heat treatment or heat treatment involving re-diffusion can be performed after both ion implantation steps are completed, only one heat treatment is required, and the depth of the outer layer is determined by this one heat treatment step. The depth of the outer layer can be controlled more accurately.

Of course, in order to create a semiconductor layer with a double structure, the first ion implantation step and the second ion implantation step are steps of imparting the same conductivity type to the semiconductor, but the ion implantation method or conditions must be changed. To achieve this, the types of impurity ions used in both ion implantation processes must be different, or even if the types of ions are the same, the ion implantation can be performed with different accelerating voltages applied to the ions. Conditions are selected.This point can be explained a little theoretically as follows.

When impurity ions of a certain type are implanted into a semiconductor at a certain acceleration voltage, there will be a distribution of impurities within the surface area of the semiconductor with a certain spread and a peak concentration at a depth corresponding to a certain range R. occurs, and the peak concentration sp is expressed by the following equation.

φ However, φ is the dose (atom/-), ΔRP is the range Rp
is the standard deviation of On the other hand, the impurity concentration distribution is a Gaussian distribution with this standard deviation ΔRp, and the impurity concentration N at a location of depth X is expressed by the following equation.

The range Rp and the standard deviation ΔR in these equations are both determined by the type of impurity ion and the accelerating voltage. A semiconductor that is ion-implanted always contains some kind of impurity, and it can be assumed that the impurity has been implanted to a point where the impurity concentration is equal to the implanted impurity concentration in the above equation. Letting the depth be xj, let x-xj in the above equation, and now the dose of P is φ-101s at an acceleration voltage of 90kV in a p-type semiconductor with an impurity concentration of N-10I & atoms/-.
If it is implanted at atoms/d, the range Rp = 0.11u
.

Since the standard deviation ΔRp-0,042is, the peak concentration NP-9,5×10' drop atom/- is obtained from the equation +1), and the ion implantation depth is 1j-0,24μ from the equation I).

Furthermore, if As is implanted as an impurity at an acceleration voltage of 80 kV and a dose of φ-5×10" atoms/-, the range R
p-0,048tna.

Since the standard deviation Δup "" is 0.017-, the peak concentration N9-I If the first ion implantation and the second ion implantation are performed using As as the impurity ion and As as the second impurity ion, the peak concentration of P in the first ion implantation step is 9.5 x 10" atoms/-. ,
Peak concentration of As in the second ion implantation step l×1
011 atoms/d can be made higher, and the As ion implantation depth in the second ion implantation step is 0.
．． 13n can be made shallow.

As can be seen from this example, by appropriately selecting the type of impurity ions and the accelerating voltage for ion implantation, the first
This makes it possible to make the ion implantation depth and impurity peak concentration in the second ion implantation step and the second ion implantation step different from each other as in the above configuration.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure shows an example in which a double semiconductor layer consisting of an n-type outer layer 12 and an inner layer N22 is formed in a p-type semiconductor 2, as shown in FIG. 2(e).

The same figure (Jl) shows the state after the completion of the mask formation step and the first ion implantation step, in which a p-type semiconductor layer 2 is diffused into an n-type substrate or epitaxial layer l, for example, as a well region for a field effect transistor. and this p
It is assumed that an n-type double-structured semiconductor layer is formed in the type layer 2, for example, for the source or drain of a field effect transistor.

In the mask forming process, an oxide film 3 is deposited on the semiconductor surface, and the oxide film 3 under the window 5a formed by the photo process in the photoresist mask 5 coated thereon is removed by etching. , followed by 0.02
A very thin oxide film 4 of about 5 μm is provided for ion implantation. As is well known, this thin oxide film is useful in preventing the crystal structure of the semiconductor surface from being irretrievably disturbed during ion implantation. In the subsequent first ion implantation step, as the first impurity ions 10, for example, P is implanted into the surface of the p-type Ji 12 at an acceleration voltage of 90 kV and a dose of 1 x 10 IS atoms/- as described above.
As a result, an ion implantation layer 11 is formed having a distribution of impurity concentration N as shown on the right side of the figure where the peak concentration Npl is 9.5 x 10'' atoms/- and the ion implantation depth x 1 is 0.24-. It should be understood that the dimension in the depth X direction of the figure is considerably exaggerated to make the figure easier to read.

(in the same figure) shows the state after the completion of the second ion implantation process,
In this step, as can be seen from the figure, with the mask 5 in its original state, the aforementioned As ions are added to the ion-implanted layer 11 as the second impurity ions 20 at an acceleration voltage of 80 kV and at a dose of 5 x 10'' atoms 71 or more. The peak concentration Np2 in this case is higher than the peak concentration Npl of the first ion implantation step (for example, as described above, the ion implantation xlQ!I atoms/d, the ion implantation depth x 2 is For example, 0.13μ is shallower than the depth Xi of the ion implantation step 1.
become. This state is shown in the diagram on the right side, and as seen in the cross-sectional view, the ion-implanted layer 21 of A3 is P
is formed inside the ion-implanted layer 11 of.

The same figure (C1 shows the state after heat treatment accompanied by re-diffusion of impurities. This heat treatment is carried out at a high temperature of 1000°C, for example, and there is a 5:1 difference in the ratio of the diffusion coefficients of P and A3 at this temperature. Therefore, by utilizing this difference in diffusion coefficient, the depth of the P ion-implanted layer 11 can be increased to the outer layer 112. As a result of re-diffusion of P, its maximum concentration Nml is equal to the previous peak concentration. The depth d of the outer layer 12 is considerably lower than
l is considerably larger than the previous depth xl of the ion implantation layer 11. On the other hand, A with a peak concentration Np2 and a depth of ×2
The ion-implanted plaster 21 of s becomes an inner layer 22 with a maximum concentration Ns+2 and a diffusion depth of d2, but since the diffusion coefficient of ^S is small, the rate of decrease in impurity concentration and the rate of increase in depth are lower than in the case of P. Therefore, although the peak concentration ratio of P and As in the ion-implanted layer was approximately 1:1O, after re-diffusion, the maximum concentration ratio increased to approximately 1 = 50, and the depth of the ion-implanted layer increased. The ratio was also about 1.8:l, but after re-diffusion it became 3.
: Increases to about 1. As a result, a semiconductor layer having a double structure in which the impurity concentration of the inner layer 22 is much higher than that of the outer layer 7123 and the depth of the outer layer 23 is obtained as shown in the figure.

In order to create an n-type double structure semiconductor layer in a p-type semiconductor layer as shown in FIG. 1, divalent P- is used as the first impurity ion in the first ion implantation step. ,
Monovalent P′ can also be used as the second impurity ion in the second ion implantation step. In this case, assuming that both impurity ions are implanted at the same accelerating voltage and dose at 90 kV and IXlOIS atoms/cd, the range Rp=0.
23 pm + standard deviation ΔR1+ -0,072-, so the peak concentration of the ion-implanted layer 11 of divalent P (see Fig. 1) is Np-5X 10" atoms/cd, and the ion implantation depth is xi- 0.53-, and the monovalent P ion implantation layer 21 is the same as before (peak concentration is Npm 9.5
Ion implantation depth x2=0.24 at X 10” atoms/-
becomes μ. Therefore, the depth ratio of the ion implantation layer 11 for the outer layer 12 and the ion implantation layer 12 for the inner layer 22 is approximately 2.
: 1. The peak concentration ratio is approximately 1:2, and since both impurities in this case are P and have the same diffusion coefficient, this ratio does not change after heat treatment, but as before, the surface impurity concentration is high and the diffusion depth is low. A large double-structured n-type semiconductor layer is obtained, and in this example, the depth of the ion implantation layer by the first ion implantation step is greater than in the previous example, so the heat treatment time can be shortened. There are advantages.

Figure 2 is the same figure (as shown in C1, there is a p-type outer layer 711 inside the n-type semiconductor substrate or epitaxial layer 1).
2 shows an example in which a double-layered semiconductor layer consisting of a semiconductor layer 2 and an inner layer 22 is fabricated. In this case, the first impurity ion is, for example, a B atom.

BFI molecules containing B are used as the second impurity ions. The mask forming process in the same figure (Jl) is the first step.
This is the same as the case shown in the figure, and in the subsequent first ion implantation step, B atoms as the first impurity ions are epitaxially implanted through a very thin oxide film 4 at an acceleration voltage of 50 kV and a dose of 1 x 10 Is atoms/-. B is implanted into layer 1, and the range of B in this case is Rp = 0.16 m, and the standard deviation is ΔRp - 0.05 Irm. The peak concentration of is Np1=8×1OI9 atoms/-
, the ion implantation depth is approximately xi -0.40 m. When one BP molecule as the second impurity ion for the second ion implantation process shown in Figure 3 is implanted at an acceleration voltage of 5゜kV and a dose of IXIG'' atoms/-, its range Rp =
0.03n, standard deviation ΔRp=0.017n,
The peak concentration of the ion implantation layer 21 is Np2-2
10" atoms/d, and the ion implantation line x2-0.12n. In this example, the ion implantation depth in the first ion implantation step is 0.4 On, and the ion implantation line is approximately 0.12n. Since it has a depth that allows it to be used almost as is, the heat treatment shown in Figure (C) is a relatively light heat treatment that does not change the impurity concentration distribution much, for example, at 400 to 600°C for about 30 minutes.
By simply activating B implanted by ion implantation as an impurity, it is possible to obtain a semiconductor layer with a double structure consisting of a p-type outer layer 7112 and a strong p-type inner layer 22. In this case, the impurity concentration ratio Nml between the outer layer 12 and the inner layer 22:
N fog 2 is approximately 1:2.5. The diffusion depth ratio di:d2 is approximately 3.3:1.

Furthermore, in FIG. 2, it is also possible to set both the first impurity ion and the second impurity ion to be B, and to vary only their acceleration voltages.

In this case, the B acceleration voltage in the first ion implantation step is, for example, 200 kV, and the dose is 1 x 10 IS atoms/-.
Then, range Rp=0.53n, standard deviation ΔRp-0
, 092n, the peak concentration of the ion implantation layer 11 is Np1
-4X10' atoms/-, ion implantation depth is xi -0
, approximately 95m. In the second ion implantation step, the B acceleration voltage is, for example, 50 kV, and the dose amount is 1 x 101.
'atom/-, the peak concentration of the ion-implanted layer 12 is 8
92-8X10' drop atom/-, ion implantation depth x2-0
．． Since it is about 40-, the impurity concentration ratio of the outer layer 12 and the inner layer 22 is 1=2. The diffusion depth ratio is approximately 2.4:1, and although the impurity concentration ratio is not so high even after a simple heat treatment, a double-structured semiconductor layer with sufficient diffusion depth can be obtained.

As mentioned above, in both the embodiments shown in FIG. 1 and FIG. 2, there is no restriction in principle on the order of the first ion implantation step and the second ion implantation step, but in general, It is advantageous to perform the first ion implantation step for the outer layer with low impurities first, since it can reduce disturbances to the crystal structure of the semiconductor. In addition, if heat treatment is not performed at high temperature for a long time as in the case of Figure 2, if ions are implanted through a thin oxide film as described above, the maximum concentration after heat treatment will be approximately equal to the peak concentration of the ion implanted layer. This is advantageous in terms of impurity concentration management. In particular, if shallow ion implantation in the second ion implantation step is performed through a thin oxide film, the peak concentration position will be very close to the interface between the semiconductor and the oxide film, which is advantageous for manufacturing the semiconductor layer under fine design rules.

An example of application of the above-described ion implantation method according to the present invention to the manufacture of a transistor will be described with reference to FIGS. 3 to 5. FIG. 3 shows an example in which the method of the present invention is applied to the source and drain of an n-channel field effect transistor. As shown in the figure, a p-type well 2 is diffused into an n-type substrate or epitaxial layer 1, A gate 6 made of polysilicon, for example, is provided on a thin gate oxide film 4 of about 0.25 m thick. Using this gate 6 and a photoresist film (not shown) as a mask,
In the first ion implantation step, P was accelerated at a voltage of 90 kV.
In the second ion implantation step, A3 was implanted at an acceleration voltage of 80 kV and a dose of 5 x 10" atoms/d at 950°C.

A high breakdown voltage source and drain having a 2N structure consisting of an n-type outer layer N12 and a strong n-type inner layer 22 are formed by a short heat treatment of about 30 minutes.

In this case, the depth of the outer layer 12 is 0.6 to 0.8 n. The protective film and electrode film are omitted to simplify the diagram, and the source S, drain D, and gate G are shown instead.
terminals are shown.

Figure 4 shows an example in which the method of the present invention is applied to the base layer of an npn bipolar transistor.
A p-type outer layer 12 and an inner layer 112 are formed on a p-type substrate l.
In the first ion implantation process, using a mask (not shown) in which a base layer with a double structure consisting of 2 and 2 is formed, B is implanted at an acceleration voltage of 50 kV and a dose of 5 x 1014 atoms/-.
In the second ion implantation process, BFt is implanted at an acceleration voltage of 50 kV and a dose of 5 x 10'4 atoms/d, and these outer surfaces are removed by a heat treatment involving re-diffusion of impurities at around 1100°C for about 1 hour. layer 12 and inner layer 22
is created. The depth of the inner layer 22 is, for example, 1.5 to 2
．． There is an emitter layer 7 within this double base layer, which is referred to as 5-.
is diffused in a strong n-type, thereby creating a vertical bipolar transistor with collector C, base B and emitter E. Since the emitter layer 7 is built into the inner layer 12 with a relatively high impurity concentration, a moderate current amplification factor is thereby obtained. In addition, since the base layer has a relatively low impurity concentration (and makes a junction with the substrate l, which is the collector layer, through the outer layer 12 with a large diffusion depth), a bipolar transistor with a high collector-base withstand voltage value can be obtained. It will be done.

FIG. 5 shows an example in which the method of the present invention is applied to the source and drain of an n-channel field effect transistor and the emitter layer and collector connection layer of an npn bipolar transistor in a BiMOS circuit. In the n-type epitaxial layer l, a well 2 is provided for the field effect transistor.
For bipolar transistors, the base layer 8 is all p.
As in the previous example of FIG. 3, the semiconductor layer of the double structure according to the present invention is pre-diffused in the form of a double-layer semiconductor layer using P as the first impurity ion and A3 as the second impurity ion.
The well 2 is used as the source and drain of the field effect transistor, the base layer 8 is used as the emitter layer of the bipolar transistor, and the epitaxial layer 1 is used as the collector connection layer. All are made in n-type. . As a result, in the field effect transistor part, the source and drain have the outer side 1112, which increases the withstand voltage value, and in the bipolar transistor part, the diffusion depth of the outer layer of the emitter layer is relatively large, so the effective base width is narrowed and the voltage is increased. A current amplification factor is obtained, and the connection resistance between the collector electrode and the collector layer 1 is reduced. Therefore, in this embodiment, while focusing on improving the withstand voltage value of the field effect transistor section, the method of the present invention can also be commonly applied to the bipolar transistor section to improve its performance.

〔Effect of the invention〕

As described above, in the present invention, the mask made in the mask forming process is also used in the first ion implantation process.

Since it is also used in the ion implantation process in step 2, the photo process for the double-layered semiconductor layer consisting of an outer layer and an inner layer can be performed only once, and the positional deviation between the outer layer and the inner layer can be avoided. Problems can be eliminated and defects can be effectively prevented from occurring. In addition, since the first ion implantation step and the second ion implantation step can be performed continuously without intervening a heat treatment step, the labor required for the ion implantation step itself can be significantly reduced compared to conventional methods. , and the heat treatment for the ion implantation layer only needs to be performed once after the completion of both ion implantation steps, thereby achieving the effect that the diffusion depth of the outer layer can be controlled more accurately than before.

The double-layered semiconductor layer formed in the semiconductor by the method of the present invention has a higher impurity concentration on the surface due to the inner layer,
Since the outer layer allows a junction with a relatively low concentration and a large diffusion depth to be obtained, it can be applied to the source and drain of a field effect transistor, the base layer of a bipolar transistor, etc. to achieve a high withstand voltage value, as shown in the example. When it is desired to carry out the present invention and obtain a double structure consisting of a deep outer layer with a low impurity concentration and a shallow inner layer with a high impurity concentration, the first ion implantation step and In the second ion implantation step, ion species having different diffusion coefficients are used, and P, which has a large diffusion coefficient, is used as the first impurity ion,
By using, for example, ^3, which has a small diffusion coefficient, as the second impurity ion, and appropriately selecting the temperature and time of the heat treatment, it is possible to form any desired 2M semiconductor layer. In addition, when applying the method of the present invention to a semiconductor layer with a fine pattern with a design rule of 2- or less, it is necessary to increase the amount of re-diffusion during heat treatment after both ion implantation steps. It is desirable to make the impurity concentration of the inner layer and the ion implantation depth sufficiently similar to each other, and for this purpose, as described in the embodiment, the first impurity ion and the second impurity ion are divalent. Ions and monovalent ions, atomic ions and molecular ions can be used, or even if the ion species are the same, the acceleration voltage for implantation can be different.

In this way, when the method of the present invention is actually applied to the production of a semiconductor device, it can be carried out in the most suitable form for the semiconductor device, and compared to the production of a normal single-layer semiconductor layer. By adding one ion implantation process, the effects of improving the withstand voltage of transistors and diodes, lowering the connection resistance with electrodes, and improving the current amplification factor can be obtained as described in the example, so semiconductor devices can be improved. This is a highly practical method that can be widely applied to increase the effectiveness of performance improvement.

[Brief explanation of the drawing]

1 to 5 relate to the present invention, and FIG. 1 shows an example in which the ion implantation method according to the present invention is applied to create an n-type double structure semiconductor layer in a p-type semiconductor. A cross-sectional view of a semiconductor layer and a corresponding impurity concentration distribution diagram shown for each main process, and FIG. A cross-sectional view of a semiconductor layer and a corresponding impurity concentration distribution diagram showing an example of each main step, and FIGS. 3 to 5 illustrate the method of the present invention for a field effect transistor, respectively. FIG. 2 is a cross-sectional view of a semiconductor layer showing an example applied to a bipolar transistor and a BiMOS circuit device. 6th rj! J is a cross-sectional view of a semiconductor layer showing each main step of a conventional method of fabricating a double-structured semiconductor layer with respect to the prior art, in Figure 0, 1: semiconductor substrate or epitaxial layer, 2: p-type layer or well, 3: Oxide film, 4: Thin oxide film for ion implantation, 5: Mask or photoresist film, 5a:
Mask window, 6: gate, 7: emitter layer, 8: base layer, lO: first impurity ion, 11: ion implantation layer by first ion implantation step, 12: outer layer of double semiconductor layer , 20: second impurity ion, 21: ion implantation layer by second ion implantation step, 22: inner layer of double semiconductor layer, 31: semiconductor substrate, 32 dioxide film, 33
, 35: Mask, 33a. 35a: mask window, 34a, 36a: ion-implanted impurity, 34: outer layer, 36: inner layer, B: base,
C: Collector, D = Nidorain dl: Diffusion depth of outer layer, d2: Diffusion depth of inner layer, E: Emitter, G: Gate, N+sl: Maximum impurity concentration of outer layer, Na3: Maximum impurity concentration of inner layer , Npl: peak impurity concentration in the ion implantation layer due to the first ion implantation process, Np2: peak impurity concentration in the ion implantation layer due to the second ion implantation process, X=depth direction, Xl: peak concentration of impurities in the ion implantation layer due to the first ion implantation process Depth of ion implantation layer x2: Depth of ion implantation layer in the second ion implantation step. (... Agent Fgert Take Yamaguchi 2・°・-1 Figure 3 Figure 5 Figure 6

Claims (1)

[Claims] 1) A method of ion-implanting an impurity that imparts a predetermined conductivity type to the surface of a semiconductor, the method comprising: depositing a mask film on the surface of the semiconductor, and then implanting the impurity into the location where the ions are to be implanted. A mask forming step in which a window is opened to serve as a mask for ion implantation, and a first ion implantation step in which first impurity ions that impart a predetermined conductivity type to the semiconductor are ion-implanted at a predetermined depth and peak concentration using this mask. an implantation step, using the same mask as in the first ion implantation step, to implant second impurity ions to give the semiconductor the same conductivity type as the first impurity ions, with a shallower and higher peak than in the first ion implantation step; An ion implantation method comprising a second ion implantation step of implanting ions at a high concentration. 2) An ion implantation method according to claim 1, characterized in that a second ion implantation step is performed after the first ion implantation step. 3) The ion implantation method according to claim 1, wherein the semiconductor is subjected to heat treatment after the first ion implantation step and the second ion implantation step. 4) An ion implantation method according to claim 3, characterized in that impurities are re-diffused into the semiconductor during heat treatment. 5) An ion implantation method according to claim 1, wherein the first impurity ion and the second impurity ion are different impurity ions. 6) The ion implantation method according to claim 5, wherein the first impurity ion and the second impurity ion are different in type of impurity element. 7) In the method described in claim 6, the predetermined conductivity type is n-type, the impurity element for the first impurity ion is P, and the impurity element for the second impurity ion is A.
An ion implantation method characterized in that s. 8) In the method described in claim 5, the first impurity ion is a monovalent impurity ion, and the second impurity ion is a divalent impurity ion of the same element as that for the first impurity ion. An ion implantation method characterized by: 9) The method according to claim 8, wherein the predetermined conductivity type is n-type, and the impurity element for the first impurity ion and the second impurity ion is P. Method. 10) In the method according to claim 5, the first
An ion implantation method characterized in that the impurity ions are atomic ions, and the second impurity ions are molecule ions containing the same element as the first impurity ion. 11) The method according to claim 10, characterized in that the predetermined conductivity type is p-type, the first impurity ion is a B atom ion, and the second impurity ion is a BF_2 molecular ion. ion implantation method. 12) In the method according to claim 1, the first
The impurity ions and the second impurity ions are the same ion, and the acceleration voltage when implanting the first impurity ions is higher than the acceleration voltage when implanting the second impurity ions. Ion implantation method. 13) The ion implantation method according to claim 12, wherein the predetermined conductivity type is p-type, and the first impurity ion and the second impurity ion are B ions. 14) In the method according to claim 1, the first
An ion implantation method characterized in that ion implantation in the ion implantation step and the second ion implantation step is performed through a very thin oxide film attached to a semiconductor surface. 15) In the method according to claim 1, the first
An ion implantation method characterized in that a source and a drain for a field effect transistor are formed into a semiconductor by the ion implantation step and the second ion implantation step. 16) In the method according to claim 1, the first
An ion implantation method characterized in that a base layer of a bipolar transistor is built into a semiconductor by re-diffusion of impurities ion-implanted in the ion implantation step and the second ion implantation step into the semiconductor. 17) In the method according to claim 1, the first
B by the ion implantation step and the second ion implantation step.
An ion implantation method characterized in that the emitter layer of a bipolar transistor and the source and drain of a field effect transistor in an iMOS circuit are simultaneously formed into a semiconductor.