JPH0510820B2 - - Google Patents
Info
- Publication number
- JPH0510820B2 JPH0510820B2 JP58114237A JP11423783A JPH0510820B2 JP H0510820 B2 JPH0510820 B2 JP H0510820B2 JP 58114237 A JP58114237 A JP 58114237A JP 11423783 A JP11423783 A JP 11423783A JP H0510820 B2 JPH0510820 B2 JP H0510820B2
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- substrate
- diffusion layer
- film
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010438 heat treatment Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 7
- 230000007547 defect Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 24
- 238000000034 method Methods 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 but in that case Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
この発明は、半導体装置の製造方法に係り、特
に半導体基板上、にイオン注入する工程を含む半
導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device including a step of implanting ions onto a semiconductor substrate.
近年、半導体集積回路の高集積化が進み、素子
寸法は、ますます小さくなつて来ている。すなわ
ち、拡散層は、より浅く、配線は、より細くなる
ことが要求されている。
2. Description of the Related Art In recent years, semiconductor integrated circuits have become more highly integrated, and device dimensions are becoming smaller and smaller. That is, the diffusion layer is required to be shallower, and the wiring is required to be thinner.
半導体集積回路では、現在、拡散層の形式は、
半導体基板に不純物をイオンとして注入した後
に、900〜1000℃の高温熱処理することによつて
活性化させる方法が行なわれている。この高温熱
処理工程は、拡散層を形成すると同時に、その
後、拡散層上に形成する金属配線との間の接触抵
抗を下げて、オーミツク接触を得る役割も果して
いる。 In semiconductor integrated circuits, the current diffusion layer format is
A method of activating the impurity by implanting impurity ions into a semiconductor substrate and then subjecting it to high temperature heat treatment at 900 to 1000 degrees Celsius is used. This high-temperature heat treatment process not only forms the diffusion layer, but also serves to lower the contact resistance with metal wiring that will be subsequently formed on the diffusion layer, thereby obtaining ohmic contact.
しかし、この高温熱処理工程は、拡散層を深く
しすぎてしまい、要求の強くなつているより浅い
拡散層を形成することは難しい。 However, this high-temperature heat treatment step makes the diffusion layer too deep, making it difficult to form a shallower diffusion layer, which is increasingly required.
本発明は、上述した問題点を改善したもので、
イオン注入した後に、700℃以下の低温で熱処理
することで要求されている浅い拡散層を形成する
と同時に、その後、拡散層上に形成する金属配線
との間でオーミツク接触を得ることを目的とす
る。
The present invention improves the above-mentioned problems, and
After ion implantation, heat treatment is performed at a low temperature of 700℃ or less to form the required shallow diffusion layer, and at the same time, the purpose is to obtain ohmic contact with the metal wiring that will be subsequently formed on the diffusion layer. .
本発明は、半導体基板上に絶縁保護膜を形成
し、該絶縁膜を写真蝕刻法によりパターニングし
て半導体基板の一部を露呈させた構造に対して、
基板の一部あるいは全面にイオンを注入し、700
℃以下の低温熱処理することで、イオンを注入し
た基板と、該構造の上に形成する金属膜との間で
オーミツク接触を得る方法を提供するものであ
る。
The present invention relates to a structure in which an insulating protective film is formed on a semiconductor substrate, and the insulating film is patterned by photolithography to expose a part of the semiconductor substrate.
Ions are implanted into part or the entire surface of the substrate, and
The present invention provides a method for obtaining ohmic contact between a substrate into which ions are implanted and a metal film formed on the structure by performing a low temperature heat treatment at temperatures below .degree.
従来は、上記の構造に対して、基板の一部ある
いは、全面にイオンとして、不純物を注入した場
合、その後の900〜1000℃の活性化熱処理工程に
よつて、キヤリア濃度を増大させて、基板とその
上に形成する金属配線との間の接触抵抗を下げ
て、オーミツク接触を得ていた。 Conventionally, when impurities are implanted in the form of ions into part or the entire surface of the substrate for the above structure, the carrier concentration is increased through a subsequent activation heat treatment process at 900 to 1000 degrees Celsius, and the substrate is Ohmic contact was obtained by lowering the contact resistance between the wire and the metal wiring formed on it.
これに対して、本発明は、イオン注入した後の
熱処理工程を650℃以下にすることによつて、イ
オン注入時に基板表面に導入された結晶欠陥、す
なわち、空孔、格子間原子等を、完全に回復させ
ることなしに、再結合中心を多いままにして、金
属配線との間の接触抵抗を下げて、オーミツク接
触を得ることを特徴としている。したがつて、注
入するイオンは、不純物とは限らず、半導体基板
それ自体と同じ材料をイオンとしてオーミツク接
触を得ることもできる。特に本発明は、金属膜を
形成する前において700℃以下の温度で熱処理す
ることが必須であり、この工程によつてオーミツ
ク接触を十分に得ることができる。即ち、金属膜
形成後に上記熱処理を行うと、該金属膜と上記基
板との間に熱応力が生じ、この熱応力によつて基
板表面に余分な結晶欠陥が導入されてしまい、上
記した効果が十分に得られないことがある。従つ
て、金属膜形成前の熱処理工程は本発明における
重要な構成要件である。 In contrast, the present invention eliminates crystal defects, such as vacancies and interstitial atoms, introduced into the substrate surface during ion implantation by performing a heat treatment process at 650°C or lower after ion implantation. It is characterized by leaving a large number of recombination centers without completely recovering, lowering the contact resistance with the metal wiring, and obtaining ohmic contact. Therefore, the ions to be implanted are not limited to impurities, and ohmic contact can also be achieved by using the same material as the semiconductor substrate itself. In particular, in the present invention, it is essential to perform heat treatment at a temperature of 700° C. or lower before forming the metal film, and this step allows sufficient ohmic contact to be obtained. That is, when the above-mentioned heat treatment is performed after forming a metal film, thermal stress is generated between the metal film and the above-mentioned substrate, and this thermal stress introduces extra crystal defects to the substrate surface, which reduces the above-mentioned effect. Sometimes you just can't get enough. Therefore, the heat treatment step before forming the metal film is an important component of the present invention.
本発明によれば、浅い拡散層を、拡散層上の金
属配線とのオーミツク接触を保つたまま、形成す
ることができる。そのために、素子の寸法を小さ
く抑えることが可能で、回路の集積度を上げるこ
とができ、今後開発が予想される超高集積回路に
利用することができる。
According to the present invention, a shallow diffusion layer can be formed while maintaining ohmic contact with metal wiring on the diffusion layer. Therefore, the dimensions of the element can be kept small, the degree of circuit integration can be increased, and it can be used in ultra-highly integrated circuits that are expected to be developed in the future.
また、今後、集積度が上がるにつれて、ゲート
配線材料として、高融点金属が使われる場合が増
えると思われるが、その場合、基板と金属との反
応あるいは、金属の酸化を防ぐ意味からゲート形
成後は、あまり高温工程を通すことができない。
したがつて、金属ゲートをイオン注入のマスクと
して用いた場合の活性化熱処理として、本発明を
応用することができる。 In addition, as the degree of integration increases in the future, it is thought that high melting point metals will be used more often as gate wiring materials, but in that case, metals with high melting points will be used after gate formation to prevent reactions between the substrate and the metal or to prevent oxidation of the metal. cannot be subjected to very high temperature processes.
Therefore, the present invention can be applied to activation heat treatment when a metal gate is used as a mask for ion implantation.
以下、本発明を適用した実施例につき、図面を
用いながら詳細に説明する。
Embodiments to which the present invention is applied will be described in detail below with reference to the drawings.
第１図に示したのは、６〜8ΩのＰ型（100）シ
リコン基板を用いてLOCOS工程で素子分離した
後に、ヒ素を加速電圧40KeVで、３×1015cm-2注
入して、600℃〜1000℃の各温度で熱処理を行な
つて形成したn+拡散層と、その拡散層上にスパ
ツター法によつて形成したAl−１％Si配線との
間の接触抵抗を測定したものである。すなわち横
軸に、各々の温度で熱処理した時間、縦軸に接触
抵抗の値を取つたものである。曲線１〜５はそれ
ぞれ熱処理温度が600℃、700℃、800℃、900℃、
1000℃の場合である。 What is shown in Figure 1 is a P-type (100) silicon substrate with a resistance of 6 to 8 Ω, which is separated by the LOCOS process, and then arsenic is implanted at 3×10 15 cm -2 at an acceleration voltage of 40 KeV. This is a measurement of the contact resistance between an n + diffusion layer formed by heat treatment at various temperatures from ℃ to 1000℃ and an Al-1%Si wiring formed on the diffusion layer by sputtering. be. That is, the horizontal axis shows the time of heat treatment at each temperature, and the vertical axis shows the contact resistance value. Curves 1 to 5 have heat treatment temperatures of 600℃, 700℃, 800℃, 900℃, respectively.
This is the case at 1000℃.
このグラフからわかるように、1000℃の高温熱
処理の場合には、注入したヒ素原子が、シリコン
結晶格子点に入つて、キヤリヤの濃度が高くなる
ことによつて接触抵抗は低い値になる。 As can be seen from this graph, in the case of high-temperature heat treatment at 1000°C, the implanted arsenic atoms enter the silicon crystal lattice points, increasing the carrier concentration and lowering the contact resistance.
しかし、熱処理温度が低い場合でも、ヒ素注入
時に破壊された結晶が完全に回復していない場合
は、再結合中心が多く存在し、接触抵抗が低くな
ることがわかる。すなわち、熱処理温度が600℃
の場合、処理時間30分以上で、1000℃熱処理の場
合と同程度の２×10-6Ωcm2の低い抵抗値を得るこ
とができた。また、600℃より結晶構造の回復し
やすい700℃の場合も、短時間熱処理することに
より、同様の接触抵抗値が得られた。したがつ
て、本発明のように700℃以下の温度の熱処理で、
拡散層と金属配線との間のオーミツク接触が可能
である。 However, even when the heat treatment temperature is low, if the crystals destroyed during arsenic implantation have not completely recovered, many recombination centers exist and the contact resistance becomes low. In other words, the heat treatment temperature is 600℃
In this case, it was possible to obtain a resistance value as low as 2×10 -6 Ωcm 2 with a treatment time of 30 minutes or more, which is comparable to the case of heat treatment at 1000°C. In addition, similar contact resistance values were obtained by short-term heat treatment at 700°C, where the crystal structure is easier to recover than at 600°C. Therefore, by heat treatment at a temperature of 700°C or less as in the present invention,
Ohmic contact between the diffusion layer and the metal wiring is possible.
第２図は、本発明を用いて作製したMOSトラ
ンジスタの断面図である。すなわち、６〜8Ωの
Ｐ型シリコン基板をLOCOS工程にしたがつて熱
酸化により、フイールド酸化膜を形成し、写真蝕
剤法により、素子領域をつくる。再び1000℃、
O2中で熱酸化して、厚さ400Åのゲート酸化膜を
形成し、その上にLPCVD法により、300Åの多
結晶シリコン膜を形成したのち、写真蝕剤法によ
り、多結晶シリコンゲート電極、およびゲート酸
化膜を素子領域に形成する(a)。この構造のまま、
ヒ素を加速電圧40KeVで、３×1015cm-2注入した
後、600℃、180分の熱処理を行ない、浅いn+拡
散層を形成する。さらにSiO2膜をCVD法により
形成した後、反応性イオンエツチングによりゲー
ト側壁にSiO2膜を残す(b)。この構造のまま、
CVD法により、ソース・ドレイン上、およびゲ
ート電極上にＷ膜を選択的に形成する(c)。この上
に、プラズマ法によりSiO2膜をかぶせて、600℃
で熱処理したのち、コンタクトホールをあけて、
アルミ配線をする(d)。以上でMOSFETが完成す
るが、浅いn+拡散層、高融点金属ゲート配線で
構成されており、寸法的に小さくすることがで
き、高集積化することが可能である。また、拡散
層を浅くすることで、抵抗が増える問題を、拡散
層上にＷをはりつけることで、解消する構造にな
つている。 FIG. 2 is a cross-sectional view of a MOS transistor manufactured using the present invention. That is, a P-type silicon substrate of 6 to 8 Ω is subjected to the LOCOS process, a field oxide film is formed by thermal oxidation, and an element region is formed by a photoetching agent method. 1000℃ again,
A gate oxide film with a thickness of 400 Å was formed by thermal oxidation in O 2 , and a polycrystalline silicon film with a thickness of 300 Å was formed on it by the LPCVD method, and then a polycrystalline silicon gate electrode, and a gate oxide film is formed in the element region (a). With this structure,
After injecting 3×10 15 cm -2 of arsenic at an acceleration voltage of 40 KeV, heat treatment is performed at 600° C. for 180 minutes to form a shallow n + diffusion layer. Furthermore, after forming a SiO 2 film by CVD, the SiO 2 film is left on the gate sidewalls by reactive ion etching (b). With this structure,
A W film is selectively formed on the source/drain and gate electrode using the CVD method (c). On top of this, a SiO 2 film was covered using the plasma method and heated to 600°C.
After heat treatment, a contact hole is made and
Make aluminum wiring (d). The above completes the MOSFET, which is composed of a shallow n + diffusion layer and a high-melting point metal gate wiring, so it can be made smaller in size and highly integrated. Furthermore, the structure solves the problem of increased resistance due to shallower diffusion layers by bonding W onto the diffusion layers.
以上、実施例として、MOSFETへの応用を示
したが、基板とその上の金属膜とオーミツク接触
を構成する半導体素子であれば、本発明を応用す
ることができる。たとえば、あらかじめ、イオン
注入後、高温熱処理で拡散層を形成した後に、シ
リコン原子をさらにイオン注入して、結晶欠陥を
導入して、接触抵抗を下げた構造の接合、トラン
ジスタを作ることもできる。 Although the application to a MOSFET has been shown as an example above, the present invention can be applied to any semiconductor element that forms ohmic contact with a substrate and a metal film thereon. For example, after ion implantation and high-temperature heat treatment to form a diffusion layer, silicon atoms can be further ion-implanted to introduce crystal defects to create a junction or transistor with a structure that reduces contact resistance.
以上のように本発明を用いれは、浅い拡散層と
拡散層上の金属配線との間でオーミツク接触を得
ることができ、超高集積回路を製作することが可
能となる。 As described above, by using the present invention, it is possible to obtain ohmic contact between the shallow diffusion layer and the metal wiring on the diffusion layer, and it becomes possible to manufacture an ultra-highly integrated circuit.
第１図は、拡散層の熱処理温度を変化させた場
合の、拡散層とその拡散層上に形成したAl−１
％Si配線との間の接触抵抗を測定した結果を示す
特性図、第２図は、本発明によるMOSFETの製
造方法の一実施例を簡略化して示す工程断面図で
ある。
１……Ｐ型シリコン基板、２……フイールド酸
化膜、３……ゲート酸化膜、４……多結晶シリコ
ン電極、５……側壁酸化膜、６……n+拡散層、
７……タングステン層、８……酸化膜、９……ア
ルミ配線。
Figure 1 shows the diffusion layer and the Al-1 formed on the diffusion layer when the heat treatment temperature of the diffusion layer is changed.
FIG. 2 is a characteristic diagram showing the results of measuring the contact resistance with the %Si wiring, and is a process cross-sectional view showing a simplified embodiment of the MOSFET manufacturing method according to the present invention. DESCRIPTION OF SYMBOLS 1...P-type silicon substrate, 2...Field oxide film, 3...Gate oxide film, 4...Polycrystalline silicon electrode, 5...Side wall oxide film, 6...N + diffusion layer,
7...Tungsten layer, 8...Oxide film, 9...Aluminum wiring.
Claims (1)
保護膜を写真蝕刻法によりパターニングして半導
体基板の一部を露呈させた構造に対して、基板の
一部或いは全面にイオンを注入することにより基
板表面に結晶欠陥を導入し、該欠陥を完全に回復
させないように700℃以下の温度で熱処理し、そ
の後、該構造の上に金属膜を形成し、イオンを注
入した基板と前記金属膜との間でオーミツク接触
を得ることを特徴とする半導体装置の製造方法。1. For a structure in which an insulating protective film is formed on a semiconductor substrate and the insulating protective film is patterned by photolithography to expose a part of the semiconductor substrate, ions are implanted into a part or the entire surface of the substrate. crystal defects are introduced into the surface of the substrate, heat treatment is performed at a temperature of 700°C or less so as not to completely recover the defects, and then a metal film is formed on the structure, and the ion-implanted substrate and the metal film are 1. A method of manufacturing a semiconductor device characterized by obtaining ohmic contact between the semiconductor device and the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11423783A JPS607126A (en) | 1983-06-27 | 1983-06-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11423783A JPS607126A (en) | 1983-06-27 | 1983-06-27 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS607126A JPS607126A (en) | 1985-01-14 |
| JPH0510820B2 true JPH0510820B2 (en) | 1993-02-10 |
Family
ID=14632695
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11423783A Granted JPS607126A (en) | 1983-06-27 | 1983-06-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS607126A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2591733B2 (en) * | 1985-10-23 | 1997-03-19 | ソニー株式会社 | Method for manufacturing semiconductor device |
| TW301032B (en) * | 1996-06-27 | 1997-03-21 | Winbond Electronics Corp | Structure of self-aligned salicide device with double sidewall spacers and fabrication method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5329668A (en) * | 1976-08-31 | 1978-03-20 | Nec Corp | Production of semiconductor device |
| JPS56146232A (en) * | 1980-02-27 | 1981-11-13 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
-
1983
- 1983-06-27 JP JP11423783A patent/JPS607126A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5329668A (en) * | 1976-08-31 | 1978-03-20 | Nec Corp | Production of semiconductor device |
| JPS56146232A (en) * | 1980-02-27 | 1981-11-13 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS607126A (en) | 1985-01-14 |
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