JPS60105250A - Method for introducing impurity - Google Patents

Abstract

PURPOSE:To obtain an MOSIC or the like with high performance and high integrity, while preventing the element properties and integrity from being degraded by a channel stopper, by selectively removing a third mask on a semiconductor substrate and by introducing an impurity into the substrate with the use of the layered mask and the third mask left on the side faces thereof. CONSTITUTION:A thin silicon oxide film 2 is formed on the surface of an N type silicon wafer 1. On this silicon oxide film 2, a layered film consisting of a lower nitride film 3 and an upper photoresist film 4 is selectively formed. A photoresist film 14 with a low viscosity is applied on the whole surface of the layered film and N type silicon wafer 1, and is etched for forming a photoresist film 15 covering the upper and side faces of the nitride film 3. After that, impurity ions of a high concentration are implanted into the surface of the N type silicon wafer 1 with the use of the nitride and photoresist film 3 and 15 as a mask. In such a manner, a channel stopper can be providing without degrading the element properties or decreasing the integrity.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applicable to semiconductor devices, particularly MISICs and bipolar ICs.
The present invention relates to a method of introducing impurities in an IC manufacturing method such as the above.

Previously, a channel stopper was used (JMf MO8IC
In manufacturing, a diffusion impurity for forming a channel stopper is ion-implanted into the entire surface using a nitride film, which is a mask for selective oxidation, and then heat treatment is performed to form a field silicon oxide film on the surface of the silicon wafer. Generally, a channel stopper diffusion layer is formed under the field silicon oxide film, and then a source, a drain, etc. are formed on the silicon wafer under the nitride film to manufacture an MO8IC.

However, the Gouyannelle stopper used in this manufacturing method is formed by penetrating into the silicon wafer region under the nitride film, which is the active region of the device, resulting in a reduction in the active region of the device and parasitic junctions caused by the channel stopper. This results in an increase in capacitance and a decrease in element breakdown voltage.

As a result, the degree of integration is reduced and device characteristics are deteriorated.

Therefore, an object of the present invention is to provide a method for introducing impurities that can prevent deterioration of device characteristics and degree of integration due to channel stoppers and can obtain semiconductor devices such as MOS ICs and bipolar ICs with high performance and high degree of integration. Our goal is to provide the following.

First, the manufacturing method of MO8IC, which is the premise of the present invention, will be explained in detail in the order of steps with reference to the drawings.

(7) The surface of the N-type silicon wafer 1 is thermally oxidized to form a thin silicon oxide film 2, and a nitride film 3 is coated on the entire surface.
It is provided by the VD method etc. (Fig. 1). Next, in order to form a pattern of the nitride film 3 serving as a mask for selective oxidation, photoetching is performed using the photoresist film 4 as a mask (FIGS. 2 and 3). The silicon oxide film 2 alleviates thermal strain and the like occurring between the silicon wafer 1 and the nitride film 3. Note that a P-type silicon wafer 1 may be used, and this manufacturing process is a known one.

The photoresist film 4 on the nitride film 3 is heat-treated to soften it, make it fluid, and extend onto the surface of the silicon oxide film 2 around the nitride film 3, forming a photoresist film 4' as shown in FIG. (1) Using the photoresist film 4' and nitride film 3 as a mask, ions of N-type impurity 5 such as phosphorus are implanted into the entire surface to form an N-type impurity.
An N-type impurity ion implantation layer 6 is provided on the surface of the type silicon wafer/.1 (FIG. 5).

The above steps (a) to (t) are the characteristics of the present invention, and the N-type ion implantation layer 6 serves as a diffusion source for forming a channel stopper diffusion layer, and the region thereof is a nitride film 3. Photoresist film 4' extending from the periphery
This is provided outside the nitride film 3 by that amount.

It is also possible to perform ion implantation to form the N-type ion implantation layer 6 after removing the silicon oxide film 2 whose surface is exposed.

) After removing the photoresist film 4' (6th
), the surface of the silicon wafer 1 is thermally oxidized using the nitride film 3 as a mask to form a field oxidized silicon film 7, and an N+ type scattering layer (channel stopper) is simultaneously provided underneath (Fig. 7). .

Since the N-type ion implantation layer 6 is formed in advance at a distance from the periphery of the nitride film 3, the channel stopper 8 is not formed at the periphery of the field silicon oxide film 7, but is formed under the field oxide silicon film 7. (9) After removing the nitride film 3 and the silicon oxide film 2, which were masks for selective oxidation, the gate silicon oxide film 9 and the polycrystalline silicon for the gate electrode are removed using well-known techniques. A film 10, a P type layer 11 serving as a source and a drain are provided by a self-alignment method (FIG. 8). Next, the entire surface is covered with an insulating film 12 such as a phosphosilicate glass film, contact windows are provided therein, and then a drain electrode D and a source electrode S are formed (FIG. 9).

As described above, since the channel stopper 8 is provided apart from the i-coupled active region, the P+ type layer 11, which is the source and drain, and the channel stopper 8 do not overlap. Therefore, the junction capacitance can be drastically reduced, and the element side pressure can be significantly improved. In addition, since the element active area can be made as small as possible, a highly integrated device can be obtained. As a law, the first
This is carried out using the 1f process as shown in FIGS. 0 to 14.

A low-viscosity photoresist film 14 is applied to the entire surface while leaving the photoresist film 4 on the nitride film 3, and the thickness of the photoresist film at the stepped portion around the periphery of the nitride film 3 is made thicker than the silicon oxide film 2. Large and thin silicon oxide film 2
After etching is performed by a plasma asher method or the like by the above film thickness, the thickness of the photoresist film extending on the surface of the silicon oxide film 2 is increased by heating and using surface tension. A photoresist film 15 having a shape is obtained.

In other words, a thin silicon oxide film 2 is formed on the surface of an N-type silicon wafer 1, and a laminated film consisting of a nitride film 3 and a photoresist film 4 is selectively formed on this silicon oxide film 2 ( Figure 10). Then, a low-viscosity photoresist film 14 is applied to the entire surface of the laminated film and the thin silicon oxide film 2 on the surface of the N-type silicon wafer 1 (FIG. 11). Then, etching is performed using a plasma asher method or the like to form a photoresist film 15 covering the top and side surfaces of the nitride film 3 (FIG. 13). Thereafter, using the nitride film 3 and the photoresist film 15 as masks, high concentration impurity ions are implanted into the surface of the N-type silicon wafer 1 (FIG. 14).

The present invention can be applied to various types of semiconductor devices such as MO8ICs, MISICs, bipolar ICs, and methods for manufacturing the same.
A channel stopper can be provided without deteriorating device characteristics or degree of integration.

[Brief explanation of the drawing]

FIGS. 1 to 9 are cross-sectional views showing the MO8IC and its manufacturing method, which are the premise of the present invention, and FIGS. 10 to 14.
The figure is a process diagram showing an example of the present invention. 1...N-type silicon wafer, 2...Silicone oxide film, 3...Nitride film, 4. 4', 13.
14゜15... Photoresist film, N-type impurity, 6... N-type impurity ion implantation layer, 7... Field silicon film, 8... Channel stock, 9... Gate silicon oxide film, 10... Gate electrode, 11... P''W layer, 12... Insulating film, D...
- Drain electrode, 5...source electrode.

Claims (1)

[Claims] 1. Selectively forming a mask for impurity introduction on the surface of a first conductivity type semiconductor substrate, and using this mask to selectively introduce impurities at a higher concentration than the semiconductor substrate into the semiconductor substrate by ion implantation. In the impurity introduction method, a stacked mask consisting of a first mask and a second mask formed on the first mask is selectively formed on the surface of the semiconductor substrate of the first conductivity type, and A third mask made of the same material as the second mask is formed extending over the surface of the semiconductor substrate on which the layered mask is not formed, and a portion of the third mask is formed on at least a side surface of the layered mask. The third mask on the semiconductor substrate on which the laminated mask is not formed is selectively removed so that the laminated mask remains, and then the impurity is removed by ion implantation using the laminated mask and the third mask remaining on the side surface of the fin. A method of introducing an impurity into the semiconductor substrate described above.