JPS60100825A - オ−ルゼロの検出回路 - Google Patents
オ−ルゼロの検出回路Info
- Publication number
- JPS60100825A JPS60100825A JP20939083A JP20939083A JPS60100825A JP S60100825 A JPS60100825 A JP S60100825A JP 20939083 A JP20939083 A JP 20939083A JP 20939083 A JP20939083 A JP 20939083A JP S60100825 A JPS60100825 A JP S60100825A
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- output
- clock signal
- gate
- logical sum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20939083A JPS60100825A (ja) | 1983-11-08 | 1983-11-08 | オ−ルゼロの検出回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20939083A JPS60100825A (ja) | 1983-11-08 | 1983-11-08 | オ−ルゼロの検出回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60100825A true JPS60100825A (ja) | 1985-06-04 |
| JPH0457130B2 JPH0457130B2 (enExample) | 1992-09-10 |
Family
ID=16572107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20939083A Granted JPS60100825A (ja) | 1983-11-08 | 1983-11-08 | オ−ルゼロの検出回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60100825A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0661814A1 (en) * | 1993-12-28 | 1995-07-05 | STMicroelectronics S.r.l. | End-of-count detecting device, particularly for nonvolatile memories |
-
1983
- 1983-11-08 JP JP20939083A patent/JPS60100825A/ja active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0661814A1 (en) * | 1993-12-28 | 1995-07-05 | STMicroelectronics S.r.l. | End-of-count detecting device, particularly for nonvolatile memories |
| US5594703A (en) * | 1993-12-28 | 1997-01-14 | Sgs-Thomson Microelectronics S.R.L. | End-of-count detecting device for nonvolatile memories |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0457130B2 (enExample) | 1992-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9146707B2 (en) | Generating a fast 3x multiplicand term for radix-8 booth multiplication | |
| US6201415B1 (en) | Latched time borrowing domino circuit | |
| JP3827947B2 (ja) | クロック異常検出装置 | |
| US4618956A (en) | Method of operating enhanced alu test hardware | |
| US6507230B1 (en) | Clock generator having a deskewer | |
| US5113363A (en) | Method and apparatus for computing arithmetic expressions using on-line operands and bit-serial processing | |
| TWI790088B (zh) | 處理器和計算系統 | |
| JPS60100825A (ja) | オ−ルゼロの検出回路 | |
| CN111030687B (zh) | 基于快速全加器的全数字锁相环及锁相控制方法 | |
| US3745315A (en) | Ripple-through counters having minimum output propagation delay times | |
| US7461305B1 (en) | System and method for detecting and preventing race condition in circuits | |
| CN114756201B (zh) | 用于实现基4 Booth乘法器的多位选择器及其实现方法、运算电路及芯片 | |
| JP2643470B2 (ja) | 同期カウンタ | |
| JPH04239819A (ja) | 同期式カウンタ | |
| CA2033428C (en) | Method and apparatus for computing arithmetic expressions using on-line operands and bit-serial processing | |
| SU1598171A1 (ru) | Четырехразр дный двоичный счетчик | |
| JP3312391B2 (ja) | n並列データのm回連続一致検出回路 | |
| JPH04291654A (ja) | 割り込み制御回路 | |
| JPH0547128B2 (enExample) | ||
| JPH0683066B2 (ja) | カウンタ回路 | |
| SU920710A1 (ru) | Сумматор последовательного действи | |
| JPS6358287A (ja) | 時間計測回路 | |
| JPS6187426A (ja) | フリツプフロツプ | |
| Seireg et al. | A general approach to the design of modulo N asynchronous counters with 50% duty cycle | |
| JPH0779247B2 (ja) | デコ−ド回路 |