JPS60100824A - Learning type digital circuit - Google Patents

Abstract

PURPOSE:To attain learning through a digital circuit by using plural memories, adders/subtractors, comparators, etc. to store at first the desired contents and then to repeat control automatically. CONSTITUTION:An adder/subtractor 1 is connected to a memory 2 to perform addition/subtraction of the contents of the memory 2. Adders 8 and 18 are connected to memories 9 and 19 for addition between the contents of these memories and the contents of the memory 2. Then comparators 10 and 20 are connected to the memories 9 and 19 to compare the contents of these memories and deliver signals when the result of comparison exceeds a fixed level. Then the desired contents are supplied first to a device through a learning input terminal 23, and a digital circuit learns relevant actions. Then the signal is supplied to an input terminal 24 to repeat those actions automatically with control.

Description

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a digital circuit having a learning function is constructed by a memory device that stores interconnections of memory devices and their strengths.

Conventionally, digital circuits have been constructed by wiring, such as soldering, in the same way as ordinary electronic circuits. However, this requires redoing the wiring every time the circuit is changed.

Furthermore, the operation of the circuit was fixed, and the series of controls were designed by humans.

The present invention, when making a digital circuit perform a series of controls, first instructs the desired output from the learning input terminal to make the circuit memorize the operation, and then automatically repeats the control. It is.

The operation will be explained below with reference to the drawings.

The memory device (2) stores the binding force, and the content increases or decreases depending on the learning results. Switch (7), (14), (12)
, (13), (15), (17), and (21) are switched at the same time.

First, switch (7), (14), (12), (13)
, (17), and (21) are at the top and the switch (15) is at the bottom, that is, the state shown in the drawing will be explained.

The value indicated by the counter (5) represents the address of any gate receiving the signal, and this value reaches the memory (19) through the switch (14).

On the other hand, the value indicated by the counter (4) represents the address of an arbitrary gate that is the sender of the signal, and is transmitted to the memory (9) through the switch (7).

The output of the memory (9) is compared in magnitude with a predetermined value by a comparator (10), and when a certain value is exceeded, a signal is issued from the gate (11).

This signal is passed through the switch (17) to the adder (18).
enables addition operations.

When the adder (18) operates, the information in the memory (19) is
The contents of the gate receiving the signal are added to the value output from the memory (2) and returned to the memory (19).

In other words, the content of the receiving gate increases by the amount of binding force. The bonding force at this time is stored in the memory (2), and the address is determined by the values of the counters (5) and (4). The content of the memory device (2) is first determined by inputting a signal corresponding to the desired output from the learning input terminal (23).
This is done by putting it in.

When a signal is input from the learning input terminal (23), the output terminal (
25), the same signal is output. If this happens, the memory device (
9) If the content is greater than a certain value and operates the comparator (10), a logical product is created by the gate (16), causing the adder/subtractor (1) to perform an addition operation.

At this time, the adder/subtractor (1) adds 1 to the contents of the memory (2), so the sender's gate in the memory (9) selected at that time and the receiver in the memory (19) This will strengthen the bond between the gates.

When counters (4) and (5) finish displaying all the gates of the sender and receiver, counter (3) operates and switches (7), (14), (12), (13) , (15), (
17) and (21) at the same time. Therefore, next, the contents of the memory (9) become the gate for the receiver, and the contents of the memory (19)
) becomes the sender. After that, repeat the same action.

The counter (3) can also periodically cause the adder/subtractor (1) to perform a subtraction operation when the number of times the switch is switched reaches a certain number. This allows connections between gates that are no longer needed to be forgotten. The input terminal (24) is a terminal that receives a signal from the outside.

[Brief explanation of the drawing]

The drawings show a block diagram of the invention. 1: Adder/subtractor 2, 9, 19: Memory device 3, 4, 5: Counter 7, 14, 12, 17, 13, 21, 15: Switch 8, 18: Adder 10, 20: Comparator 11, 22: OR gate 16: AND gate 23: Learning input terminal 24: Input terminal 25: Output terminal

Claims (1)

[Claims] (a) An adder/subtractor (1) is connected to the memory (2) so as to add and subtract the contents thereof. (b) The memory devices (9) and (19) each have an adder (8) so that their contents and the contents of the memory device (2) can be added together.
) and (18). (c) The memories (9) and (19) are equipped with a comparator (1) that compares the contents and outputs a signal when a certain value is exceeded.
Connect 0) and (20). (d) The comparators (20) control the adder (8), and the comparators (10) are connected alternately so as to control the adder (18). (e) The AND of comparators (10) and (20) is performed by the gate (
16) and connect it to control the adder/subtractor (1). (F) The oscillator (6
) and counters (3), (4), and (5). A learning type digital circuit configured as described above.