JPS60100211A - Programmable controller - Google Patents

Programmable controller

Info

Publication number
JPS60100211A
JPS60100211A JP20791383A JP20791383A JPS60100211A JP S60100211 A JPS60100211 A JP S60100211A JP 20791383 A JP20791383 A JP 20791383A JP 20791383 A JP20791383 A JP 20791383A JP S60100211 A JPS60100211 A JP S60100211A
Authority
JP
Japan
Prior art keywords
shift register
section
data
shift
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20791383A
Other languages
Japanese (ja)
Inventor
Soji Oota
太田　宗司
Toshio Morimoto
敏夫 森本
Kazuyuki Yamamoto
和幸 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP20791383A priority Critical patent/JPS60100211A/en
Publication of JPS60100211A publication Critical patent/JPS60100211A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/054—Input/output

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To obtain a programmable controller with a wide range of use by setting data for dividing a shift register in a shift register controller. CONSTITUTION:The state of connected input equipment is inputted at an input part 1 and processed logically by a control part 2. The result is displayed at a display part 4 and sent to an output part 5. Necessary data is stored in a storage part 6 and an operation part 3 sends a command to said control part 2. The shift register controller 7 in this storage part 6 consists of a division data part for storing the data which divides shift registers in the storage part 6 optionally, a resetting part which resets it, a part DOWN, and a part UP. Consequently, the shift register is divided into (n) stages N/n, and each bit of each shift register is shifted up or down by one stage when said part UP or DOWN varies from 0 to 1.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は記憶部内のシフトレジスタを任意の個数に分割
し、同時にシフトする複数個のシフトレジスタとして使
用可能とし、記憶部を有効に使うことのできるプログラ
マブルコントローラに関するものである。[Detailed Description of the Invention] Industrial Application Field The present invention divides a shift register in a storage unit into an arbitrary number of units, and makes it possible to use it as a plurality of shift registers that shift simultaneously, thereby making it possible to effectively use the storage unit. This invention relates to a programmable controller.

従来例の構成とその問題点 従来のプログラマブルコントローラはシフトレジスタを
内蔵してはいたが、／フトレジスタの個数が固定であっ
た。このような従来のプログラマフルコントローラでは
、シフトレジスタが多数必要な場合にはプログラマブル
コントローラ内部もしくは外部に多数のシフトレジスタ
を存在させておく必要があり、記憶部内で広範囲の領域
が必要になる。また操作が複雑であるという欠点を有し
ていた。Conventional configuration and its problems Conventional programmable controllers have built-in shift registers, but the number of shift registers is fixed. In such a conventional programmable controller, if a large number of shift registers are required, it is necessary to have a large number of shift registers inside or outside the programmable controller, and a wide area is required in the storage unit. It also has the disadvantage of being complicated to operate.

発明の目的 本発明は上記従来の欠点を解消し、記憶部内のシフトレ
ジスタを任意の個数に分割し、同時にシフトする複数個
のシフトレジスタとして使用できるようにしたプログラ
マブルコントローラを提供するものである。OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned conventional drawbacks and provides a programmable controller in which a shift register in a storage section is divided into an arbitrary number of shift registers and can be used as a plurality of shift registers that shift simultaneously.

発明の構成 本発明のプログラマブルコントローラＩｄ：、　シー　
’ｙンスプログラムによりシフトレジスタを分割するデ
ータを入力させ、制御部を介して記憶部に格納し、前記
記憶部内のシフトレジスタを入力されたデータに従い分
割するように構成したものである。Configuration of the invention Programmable controller Id of the invention:
The system is configured such that data for dividing the shift register is inputted by a program, and stored in a storage section via a control section, and the shift register in the storage section is divided according to the input data.

実施例の説明 第１図は本発明の一実施例を示すブロック図である。１
は外部に接続された入力機器の状態を入力する入力部で
、２は入力機器の状態や内部情報に対して論理演算を行
なう制御部で、３は制御部２に指令を送る操作部で、４
は制御部２に処理された演算結果や入出力状態等を表示
する表示部で、５は制御部２で処理された結果を外部に
接続された出力機器に出力する出力部で、６は制御部２
が必要なデータを格納しておく記憶部である。第２図の
７は記憶部６内に存在するシフトレジスタコントロール
で、記憶部６内のシフトレジスタを任意に分割するため
のデータを格納する分割データ部と、前記シフトレジス
タをオールＯにするデーするＤ　Ｏ’Ｗ　Ｎ部と、前記
シフトレジスタの各ピノ＃【 トを上位希にシフトさせるデータを格納するＵＰ部とで
構成されている。第３図は本考案要部のフローチャート
である０ステツプ８でシフトレジスタコントロール７内
のり七ノド部が１かどうかを判断し、もし１であるなら
ばステップ９でシフトレジスタをオール０にする。また
１でないならばステ、プ１０で分割データが何であるか
を判断しステップ１１で分割データに従いシフトレジス
タを分割する。次にステップ１２でシフトレジスタコン
トロール７内のＵＰ部が１かどうか判断し、もし１なら
ばステップ１３でシフトレジスタの各殴 ビットを１ビツト」二位軒にシフトするｏｌでないなら
ばステップ１４でシフトレジスタコントロール７内のＤ
ＯＷＮ部が１かどうか判断し、もし１ならばステ、グ１
５でシフトレジスタ内の各ピノを更 トを１ピント下位岨／フ卜する。１でないならば実行終
了とする０またシフトレジスタコントロール内のＵＰ部
とＬ）　Ｏ’Ｗ　Ｎ部が同時に１になるときには何もし
ない０ 第４図において、１６はシフトレジスタコントロール７
にデータを入力したものである。ここで分割データは任
意の数ｎである。１７は分割前のＮビットのシフトレジ
スタであり、ｎビットで構成されているデータが入力し
である。１８はデータを各々専用のシフトレジスタに振
分けるために分割した後のシフトレジスタの状態である
。ここでシフトレジスタはｎ段Ｎ　／　ｎ列に分割され
ている。各々のシフトレジスタはシフトレジスタコント
ロールＹ内のＵＰ部あるいはＤＯＷＮ部が０がされるタ
イミングは同時である。DESCRIPTION OF THE EMBODIMENT FIG. 1 is a block diagram showing an embodiment of the present invention. 1
is an input unit that inputs the status of an externally connected input device, 2 is a control unit that performs logical operations on the status of the input device and internal information, and 3 is an operation unit that sends commands to the control unit 2. 4
5 is a display unit that displays the calculation results processed by the control unit 2, input/output status, etc., 5 is an output unit that outputs the results processed by the control unit 2 to an output device connected to the outside, and 6 is a control unit. Part 2
is a storage unit that stores necessary data. Reference numeral 7 in FIG. 2 is a shift register control that exists in the storage unit 6, which includes a division data section that stores data for arbitrarily dividing the shift register in the storage unit 6, and a data section that stores data for arbitrarily dividing the shift register in the storage unit 6. and an UP section that stores data for shifting each pinot of the shift register to the uppermost position. FIG. 3 is a flowchart of the main part of the present invention. At step 8, it is determined whether or not the 7th node part in the shift register control 7 is 1. If it is 1, the shift register is set to all 0s at step 9. If it is not 1, it is determined in step 10 what the divided data is, and in step 11 the shift register is divided according to the divided data. Next, in step 12, it is determined whether the UP part in the shift register control 7 is 1, and if it is 1, in step 13, each punched bit of the shift register is shifted by 1 bit to the second position.If not, in step 14, D in shift register control 7
Determine whether the OWN part is 1, and if it is 1, step, group 1
Step 5 changes each pin in the shift register to one lower pin. If it is not 1, the execution ends. 0 Also, if the UP part and L in the shift register control and the O'W N part become 1 at the same time, do nothing. 0 In Fig. 4, 16 is the shift register control 7
The data was entered into . Here, the number of divided data is an arbitrary number n. Reference numeral 17 denotes an N-bit shift register before division, into which data composed of n bits is input. 18 is the state of the shift register after the data is divided to be distributed to each dedicated shift register. Here, the shift register is divided into n stages and N/n columns. In each shift register, the UP part or DOWN part in the shift register control Y is set to 0 at the same time.

発明の効果 本発明はシフトレジスタコントロールにシフトレジスタ
を分割するためのデータ、シフトする方向を任意に設定
できるので、記憶部内のシフトレジスタの領域が削減で
き、使用範囲の広いシフトレジスタを有するプログラマ
プルコントローラヲ恒１４＋斗ト　ｙａｎｚ−ｙｘ　シ
　７Effects of the Invention The present invention allows the shift register control to arbitrarily set the data for dividing the shift register and the shifting direction, thereby reducing the area of the shift register in the storage unit and providing a programmer with a shift register that can be used in a wide range of applications. Controller 14 + yanz-yx 7

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例のブロック図、第２図は本実
施例内蔵のシフトレジスタコントロールの構成図、第３
図は本実施例要部のフローチャート図、第４図は同要部
の具体例の説明図である。 １・・・・・・入力部、２・・・・・・制御部、３・・
・・・・操作部、４・・・・・表示部、５・・・・・・
出力部、６・・・・記憶部。 代理人の氏名　弁理」−中　尾　敏　男　ほか１名第１
図 第２図 第３図Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a configuration diagram of a shift register control built in this embodiment, and Fig. 3 is a block diagram of an embodiment of the present invention.
The figure is a flowchart of the main part of this embodiment, and FIG. 4 is an explanatory diagram of a specific example of the main part. 1...Input section, 2...Control section, 3...
...Operation unit, 4...Display section, 5...
Output section, 6...Storage section. Name of Agent: Patent Attorney - Toshio Nakao and 1 other person 1st
Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 入力機器の状態を入力する入力部と、入力の状態や内部
情報に対して論理演算を行なう制御部と、制御部で処理
された結果を出力機器に出力する出力部と、入力情報や
処理結果等を格納しておく記憶部と、前記制御部に各種
指令を送る操作部と、前記操作部で指示された各種指令
や前記制御部で処理された結果等を表示する表示部とか
らなり、前記記憶部内に存在するシフトレジスタを任意
の個数に分割し、同時にシフトする複数個のシフトレジ
スタとして使用できることを可能としたプログラマフル
コントローラ。An input section that inputs the state of the input device, a control section that performs logical operations on the input state and internal information, an output section that outputs the results processed by the control section to the output device, and input information and processing results. an operating section that sends various commands to the control section, and a display section that displays various commands instructed by the operating section, results processed by the control section, etc., A programmer full controller that allows the shift register existing in the storage unit to be divided into an arbitrary number of parts and used as a plurality of shift registers that shift simultaneously.
JP20791383A 1983-11-04 1983-11-04 Programmable controller Pending JPS60100211A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20791383A JPS60100211A (en) 1983-11-04 1983-11-04 Programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20791383A JPS60100211A (en) 1983-11-04 1983-11-04 Programmable controller

Publications (1)

Publication Number Publication Date
JPS60100211A true JPS60100211A (en) 1985-06-04

Family

ID=16547636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20791383A Pending JPS60100211A (en) 1983-11-04 1983-11-04 Programmable controller

Country Status (1)

Country Link
JP (1) JPS60100211A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999011552A1 (en) * 1997-09-02 1999-03-11 Diesse S.R.L. A method for levelling and/or turning one or more stacks of sheet material arranged on a base or pallet and an independent unit for implementing said method and moving said stacks

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999011552A1 (en) * 1997-09-02 1999-03-11 Diesse S.R.L. A method for levelling and/or turning one or more stacks of sheet material arranged on a base or pallet and an independent unit for implementing said method and moving said stacks

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