JPH05274012A - Input/output allocation variable programmable controller - Google Patents

Abstract

PURPOSE:To provide an input/output allocation variable programmable controller which can occasionally change and set the allocation of an input/output memory to an input/output device. CONSTITUTION:A value setting part 107 of a CPU part 100 inputs the memory conditions set by the screen display to a display part 140. A memory condition setting part 103 sets the head address and the boundary value of the inputted digital input/output data at the storage parts DT and DB and the head address and the boundary value of the analog input/output data at the storage parts AT and AB respectively. A data table part 104 calculates an address AD from a numerical expression DT+DBXPN=AD or AT+ABXPN=AD based on the set memory conditions DT, DB, AT and AB and the device number PN of each of input/output devices 120-i (i=1, 2n) of an input/output part 120. Then the addresses AD are allocated to 100 device numbers (0-99) so that a data input/output table is obtained. The part 100 performs the input/output of data between the devices 120-i and the addresses of an input/output memory which are allocated to the device numbers based on the data input/output table.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller, and more particularly, to an input / output assignment variable programmable controller capable of changing the address assignment of a memory input / output area to an input / output device.

[0002]

2. Description of the Related Art Generally, a programmable controller (hereinafter referred to as a PC) has a configuration as shown in FIG.
CPU (Central Processing Unit) for calculation and control
I / O for inputting / outputting input / output data to / from a plurality of controlled devices under the control of the unit 401 and its CPU unit 401.
It is divided into a part 420. The I / O unit 420 and CP
The U section 401 is connected via a bus 410.

The CPU section 401 is an arithmetic section 404 operated by a user program, an I / O memory 402 for storing data input / output between the arithmetic section 404 and the I / O section 420, and its I / O memory 402. Is composed of an I / O buffer 403 that temporarily stores data to be input / output.

The I / O unit 420 comprises I / O devices (interfaces) 420-1, 420-2, ... 420-n for inputting / outputting input / output data to / from a plurality of controlled devices. Those I / O devices 420-i (i = 1, 2, ...
n) are station number setters 430-i (i = 1, 2 ...
..N), and the station number setter 430-i has each I / O
Two-digit device number (station number) assigned to O device 430-i
Is set.

The CPU section 401 receives data input from each I / O device 420-i of the I / O section 420 via the bus 410, and outputs data to the I / O buffer 403 and the I / O memory 4.
02 to the arithmetic unit 404, the arithmetic operation is performed using the input data, and the arithmetic result is input to the I / O memory 40.
2, I / O buffer 403, and I via the bus 410
By outputting to the I / O device 420-i of the I / O unit 420, the controlled device connected to the I / O device 420-i is controlled.

In the above-mentioned data input / output, the address of the I / O memory 402 is previously set in each of the I / O devices 430-.
It is set to correspond to the station number assigned to i,
Based on the setting, data is input / output between the address of the I / O memory 402 and the I / O device 430-i corresponding to the address.

The I / O device 420-i (i = 1, 2 ...
..N) are configured with various different combinations corresponding to the controlled devices that differ depending on the field of operation of the PC. Therefore, the specification of I / O allocation for associating the address of the I / O memory 402 with the I / O device 420-i also varies depending on the field of operation of the PC.

FIG. 7 shows an example of a conventional I / O allocation specification. The I / O memory 402 'shown in FIG.
Up to a total of 100 memory station numbers represented by two digits of "99" are set. The data boundary (boundary) of one memory station number is set to 1 word, and the address is I /
Corresponding in ascending order for each word from the beginning of the O memory 402 '.

In the figure, the I / O device 420-1 is
The input / output data is 2 words and the device station number is set to "00". The I / O device 420-1 has two memory station numbers (two words) of a memory station number "00" of the I / O memory 402 'corresponding to the device station number "00" and a subsequent memory station number "01". Is assigned.

In the next I / O device 420-2, the memory station number "01" and the memory station number "00" together with the I
Since it has been assigned to the / O device 420-1, the device station number “02” corresponding to the next memory station number “02” is assigned. Since the input / output data of the I / O device 420-2 is one word, only the memory station number “02” (for one word) is assigned.

In the I / O device 420-n, the device station number is set to "31" and the input / output data is 8 words. Therefore, the memory station numbers "31" to "3" of the I / O memory 402 'corresponding to the device station number "31" are changed.
8 memory station numbers (8 words) up to 8 "are assigned.

In the allocation example shown in the figure, for example, all I / O
If the input / output data of the device 420-i is 16 words,
The number of I / O devices that can be assigned to the I / O memory 402 'is 100 memory station number (= 100 words) ÷ 16 words = 6.25, that is, six. Also, all I / O
If the input / output data of the device 420-i is 1 word, the number of I / O devices that can be assigned to the I / O memory 402 'is 100 memory station number (= 100 words) / 1.
Word = 100, that is, 100 words.

Next, FIG. 8 shows another example of the conventional I / O allocation specification. The storage area of the I / O memory 402 ″ includes, for example, a digital I / O memory area 402 ″ -D that controls sorting of product numbers and the like, and an analog I / O memory area 402 ″-that controls, for example, power voltage. It is divided into two A. The divided storage areas are each "00".
From 32 to "31", 32 memory station numbers are set.
The data boundary (boundary) of the memory station number of the digital I / O memory area 402 ″ -D is set to 4 words, and the boundary of the memory station number of the analog I / O memory area 402 ″ -A is set to 16 words. In this case also, the addresses correspond in ascending order word by word from the beginning of the I / O memory 402 ″.

In the figure, the I / O device 420-1 is a digital I / O device, and the device station number is "0" as described above.
It is set to "0" and the input / output data is 2 words. The I / O memory 40 corresponding to the device station number "00"
The memory station number "00" of the 2 "digital I / O memory area 402" -D is allocated.

The I / O device 420-2 is also a digital I / O device, and the device station number is "0" as described above.
If "2" is set and the input / output data is 1 word, the I / O memory 40 corresponding to the device station number "02"
The memory station number “02” of the 2 ″ digital I / O memory area 402 ″ -D is allocated. In this example, the memory station number "01" of the digital I / O memory area 402 "-D is unused. Of course, the device station number of the I / O device 420-2 can be set to "01" and the memory station number "01" can be assigned.

The I / O device 420-n is an analog I / O device, and the device station number is "3" as described above.
It is set to "1" and the input / output data is 8 words. In this case, the analog I / O of the I / O memory 402 ″ is
It is assigned to the memory station number “31” of the O memory area 402 ″ -A.

A digital I / O device and an analog I / O device
Since the same device station number cannot be set for the I / O device, in the above case, the digital I / O device and the analog I / O device
Up to 32 I / O devices can be allocated for the O devices in total.

Input / output of data between the CPU unit 401 and the I / O unit 420 shown in FIG. 6 indicates whether the I / O device 420-i is a digital I / O device or an analog I / O device. The I / O memory 402 '(or 40) is based on the division data, the start address, the boundary value, and the device station number.
2 ") is calculated to correspond to the memory station number assigned to the I / O device, and data input / output is performed.

As described above, conventionally, different I / O allocations have been set and operated according to the use of each PC.

[0020]

In the example of the first memory allocation shown in FIG. 7, when the number of words of input / output data of the I / O device becomes large, the second memory shown in FIG. There is a problem that the number of connectable I / O devices is extremely small compared to the allocation example. For example, if the input / output data of all I / O devices is 16 words, in the second memory allocation example, 32 words of 16-word memory area are set.
Whereas, in the first memory allocation example, 100 memory station numbers (= 100 words) / 16 words = 6.25, that is, only six I / O devices can be connected. .. Therefore, an I / O device with a large number of words must be
There is a disadvantage that the PC cannot be operated when it is necessary to connect more than the number of the PCs.

On the other hand, in the second example of memory allocation,
I / O device, regardless of the number of input / output words
There is a problem that the number of connectable O devices is limited. For example, when the input / output data of all the I / O devices becomes 1 word, 100 is set in the first memory allocation example.
Memory station number (= 100 words) ÷ 1 word = 100, and the number of connectable I / O devices is 100, whereas in the second memory allocation example, 4 words 32 stations and 16 words 32 Since only one of the stations is assigned so that the station number does not overlap, only 32 I / O devices can be connected. Therefore, in this case, when it becomes necessary to connect more than 32 I / O devices, the P
There was a problem that C could not be operated, and there were various problems.

An object of the present invention is to provide I / O for I / O devices.
An object of the present invention is to provide an input / output assignment variable programmable controller in which the input / output assignment of O memory can be changed and set at any time.

[0023]

Means and Actions for Solving the Problems Means and actions of the present invention are as follows. According to the first aspect of the invention, the digital boundary value setting means 1 sets a boundary value in the memory input / output area of data input / output to / from a plurality of digital input / output devices each having a device number.

The digital address setting means 2 sets the start address of the input / output data for the plurality of digital input / output devices. Digital table generating means 3
Is based on the device number of each of the plurality of digital input / output devices, the boundary value set by the digital boundary value setting means 1, and the start address set by the digital address setting means 2. A digital input / output data allocation table in which the device numbers of the input / output devices correspond to the addresses of the memory input / output area is generated.

The digital input / output means 4 inputs / outputs data to / from the plurality of digital input / output devices based on the digital input / output data allocation table generated by the digital table generating means 3.

As a result, the allocation of the input / output memory for each digital input / output device can be changed at any time, and digital input / output data can be input / output by the changed input / output allocation.

According to the second aspect of the present invention, the analog boundary value setting means 5 sets the boundary value in the memory input / output area of the data input / output to / from the analog input / output device each having the device number.

The analog address setting means 6 sets the start address of the input / output data for the plurality of analog input / output devices. The analog table generating means 7 is based on the device number of each of the plurality of analog input / output devices, the boundary value set by the analog boundary value setting means 7, and the start address set by the analog address setting means 6. An analog input / output data allocation table in which the device numbers of the plurality of analog input / output devices correspond to the addresses of the memory input / output area is generated.

The analog input / output means 8 inputs / outputs data to / from the plurality of analog input / output devices based on the analog input / output data allocation table generated by the analog table generating means 7.

As a result, the allocation of the input / output memory for each analog input / output device can be changed at any time, and analog input / output data can be input / output by the changed input / output allocation.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the programmable controller according to the first embodiment.

In the figure, a programmable controller 10 is a CPU (Central Process) that performs calculation and control.
ing unit) 100 and an I / O unit 120 for inputting / outputting data to / from a plurality of input / output controlled devices under the control of the CPU unit 100. The I / O section 12
0 and the CPU unit 100 are connected via a bus 110.

The CPU section 100 has a predetermined operation section 101 that operates according to a user program, a flag register section 102 that is set to ON or OFF when the system is set up, and an ON / OFF state of the flag register section 102. Memory condition setting unit 10 for setting memory conditions
3, a data table unit 104 that creates and stores a data input / output table based on the memory condition set in the memory condition setting unit 103, and the data table unit 104
The data input / output between the arithmetic unit 101 and the I / O unit 120 based on the data input / output table stored in
The I / O device and the I / O memory 105 that stores the I / O device in association with the memory storage area allocated to the I / O device and the input / output data thereof are temporarily stored, and the I / O memory 105
I / O buffer 1 for inputting / outputting data to / from the I / O unit 120
It consists of 06.

The I / O unit 120 is an I / O device (interface) for inputting / outputting data to / from a plurality of input / output controlled devices.
120-1, 120-2 ... 120-n. Those I / O devices 120-i (i = 1, 2, ... N)
Are device station number setting devices 130-i (i = 1, 2, ...
..N) and their device station number setting device 130
A 2-digit device station number is set in -i.

3A, 3B and 3C, the CPU section 100 is shown.
Flag register unit 102, memory condition setting unit 103,
3 shows the data structure of the data table unit 104. First, the flag register unit 102 shown in FIG. 9A stores ON or OFF information set at the time of system setup.

Next, the memory condition setting unit 103 shown in FIG. 7B is composed of a memory DB 103-1 and a memory DT 103-.
2, memory AB103-3, and memory AT103-4
4 memory areas. The memory DB 103-
1 stores the boundary value of the digital I / O input / output data, and the memory DT103-2 stores the start address of the digital I / O input / output data. Also, the memory AB1
03-3 stores the boundary value of the analog I / O input / output data, and the memory AT 103-4 stores the start address of the analog I / O input / output data.

The boundary value corresponds to a fixed length field such as a halfword or a doubleword, and is stored in the main memory (I
/ O memory 105) represents a memory definition boundary of an information unit given, for example, in the case of FIG. 7 in the conventional example, the data boundary value is “1”. In the case of FIG. 8 of the conventional example, the data boundary value of the digital input / output data area is “4”, and the boundary value of the data of the analog input / output data area is “16”.

In this embodiment, when the flag register unit 102 is on, the memory DB 103-1 is "1", the memory DT103-2 is "0", and the memory AB is "1".
“1” is stored in 103-3, and “0” is stored in the memory AT 103-4. On the other hand, when the flag register unit 102 is off, “4” is stored in the memory DB 103-1, “0” is stored in the memory DT103-2, “16” is stored in the memory AB103-3, and “4” is stored in the memory AT103-4. 128 "
Is memorized.

Next, the data table section 104 shown in FIG. 3C will be described. The data table section 104 is
It has a data input / output table composed of 100 device station numbers from "0" to "99" and the addresses of the I / O memory assigned to the device station numbers. The address of the I / O memory that constitutes this data input / output table is calculated by the operation described below, and is assigned corresponding to each device station number.

That is, the memory address corresponding to each device station number is calculated by the mathematical expression DT + DB × PN = AD for the digital I / O device and the mathematical expression AT + AB × PN = AD for the analog I / O device. Here, DT is the start address of the digital input / output data area set in the memory DT103-2, DB is the boundary value of the digital input / output data set in the memory DB103-1, and PN is the I / O device 120-i. The station number set in the device station number setter 130-i, AT is the start address of the analog input / output data area set in the memory AT103-3, AB is the boundary value of the analog input / output data set in the memory AB103-4, And AD are memory addresses calculated by calculation.

Next, regarding the operation of the embodiment having the above configuration,
explain. First, the case where the flag register unit 102 is set to ON when the system starts up will be described. When the flag register unit 102 is on, the memory DB 103-1 is set to "1" (hereinafter, described as DB = 1), DT = 0, AB = 1 and AT = 0.

Therefore, for example, the I / O device 120-1
Is a digital I / O device and the device station number is “00”, 0 (DT) +1 (DB) × 00 (PN) = 0 is calculated by the above formula DT + DB × PN = AD. That is, the I / O device 12 with the device station number "00"
The memory address AD assigned to 0-1 is calculated as "00", and the address "00" is set corresponding to the device station number "00" in the data input / output table shown in FIG. 3 (c).

If the I / O device 120-2 is also a digital I / O device and the device station number is "02", the formula DT + DB × PN = AD also gives 0 (D
T) +1 (DB) × 02 (PN) = 2 is calculated. That is, the memory address AD assigned to the I / O device 120-2 having the device station number “02” is calculated as “02”. Then, in the data input / output table, the device station number "0
The address "02" is set in correspondence with "2".

Further, assuming that the I / O device 120-n is an analog I / O device and the device station number is "31", the above formula AT + AB * PN = AD is used in this case. Then, 0 (AT) +1 (AB) × 31 (P
N) = 31 is calculated, and the memory address AD assigned to the I / O device 120-n having the device station number “31” is “3”.
1 ", and the device station number" 3 "in the data input / output table
The address "31" is set in correspondence with "1".

Each time the CPU unit 100 shown in FIG. 2 inputs / outputs data, the data input / output table of the set data table unit 104 is referred to, and the memory area for storing the input / output data is the data input / output table. It is determined by the address above and the number of words of the I / O device, and the I / O device 120-i corresponding to the address is also determined by the device station number of the data input / output table to determine the I / O device and the memory area. Will be assigned. That is, as described above, the address "00" is assigned to the I / O device station number "0".
0 ”, but the address“ 02 ”is the I / O device station number“ 02 ”
However, the address "31" is the I / O device station number "31",
Each is assigned.

As described above, in this embodiment, as in the conventional example of FIG. 7, when the boundary value is "1" and the memory start address of the input / output data for both digital and analog is "00", I It is possible to realize the same I / O allocation to the I / O device 120-i as in the conventional example of FIG.

Next, the operation when the flag register unit 102 is set to OFF when the system starts up will be described. When the flag register unit 102 is off, D
B = 4, DT = 0, AB = 16 and AT = 128 are set.

Also in this case, assuming that the I / O device 120-1 is a digital I / O device and the device station number is "00", the formula DT + DB × PN = AD gives 0 (D
T) +4 (DB) × 00 (PN) = 0 is calculated. That is, the memory address AD assigned to the I / O device 120-1 having the device station number “00” is calculated as “00”. Then, the address "00" is set corresponding to the device station number "00" in the data input / output table shown in FIG. 3 (c).

If the I / O device 120-2 is also a digital I / O device and the device station number is "02", then 0 (D
T) +4 (DB) × 02 (PN) = 8 is calculated. That is, the memory address AD assigned to the I / O device 120-2 having the device station number “02” is calculated as “08”,
The address "08" is set corresponding to the device station number "02" in the data input / output table.

Further, assuming that the I / O device 120-n is an analog I / O device and the device station number is "31", in this case, the formula AT + AB × PN = AD gives 1
28 (AT) +16 (AB) × 31 (PN) = 624 is calculated. That is, the memory address AD assigned to the I / O device 120-n having the device station number “31” is “62”.
4 ”, and the device station number“ 3 ”in the data input / output table
The address "624" is set in correspondence with "1".

Therefore, in this case, the CPU section 100
Each time data is input or output by the I / O device, the I / O device station number “00” is assigned the address “0” based on the data input / output table.
0 ”is the address“ 08 ”for the I / O device station number“ 02 ”
However, the address "128" is assigned to the I / O device station number "31".
Are assigned respectively.

As described above, in the present embodiment, the boundary value is "4" for digital input / output data, "16" for analog input / output data, and digital input / output data as in the conventional example of FIG. Even when the memory start address is "00" and the analog input / output data memory start address is "128", the same I / O allocation as in the conventional example of FIG. 8 is performed on the I / O device 120-i. realizable.

In the above embodiment, two sets of set values are set in advance for the boundary value and the start address of the digital input / output data and the analog input / output data, respectively, and the above-mentioned 2 is set based on the ON / OFF state of the flag register 102. Although one set of set values is selected from the set of set values, the set values may be arbitrarily set without being determined in advance. This will be described below as another embodiment.

FIG. 4 is a block diagram showing the configuration of the programmable controller according to the second embodiment. In the figure, the same components as those of the first embodiment shown in FIG. 2 are designated by the same reference numerals. In the CPU section 101,
The flag register unit 102 shown in the first embodiment is removed, and a set value setting unit 107 is provided. The set value setting unit 107 is connected to an externally provided display unit 140 including, for example, a liquid crystal panel. Other configurations are the first
Is the same as the embodiment described above.

FIG. 5 shows an example of a display screen displayed on the display section 140. This display is displayed by the set value setting unit 107, for example, by reading the display data stored in advance in another data area of the memory 105 when the system starts up.

In the figure, an "I / O allocation setting screen" indicating that this display is a display screen for I / O memory allocation setting is displayed above the screen of the display unit 140, and below it. In the first row, a "digital I / O memory boundary set value" indicating what the set value to be input is, an enclosure for displaying the input set value, and the set value are stored. “DB” indicating the memory area is displayed. In the second row, the "digital I / O memory start address set value" that also indicates what the set value should be input, an enclosure for displaying the input set value, and the set value are stored. "DT" indicating the memory area
Is displayed. Similarly, in the third row, "Analog I
/ O memory boundary set value ”, enclosure, and“ AB ”
Is displayed, and the "analog I / O memory start address set value", a surrounding frame, and "AT" are displayed in the fourth row.

Although not particularly shown, the set value setting section 107 is connected to a keyboard having a ten-key pad, a cursor key, etc., and the cursor key is used to move one of the boxes in the enclosure.
One of them is selected, and the set value corresponding to the selected surrounding frame display portion is input by the ten keys. These input set values are stored in each memory area (memory DB 103-1, DT 103-2, AB) by the memory condition setting unit 103.
103-3 and AT 103-4).

As a result, it is possible to set arbitrary boundary values and start addresses for the digital input / output data and the analog input / output data. Based on these set boundary values and start addresses, the addresses of the I / O memory corresponding to the device station number are calculated by the above-described calculation, and these calculated addresses are stored in the data input / output table of the data table unit 104. Then, it is set corresponding to each device station number.

Then, as in the first embodiment, every time the CPU section 100 shown in FIG. 2 inputs / outputs data, the data input / output table of the set data table section 104 is referred to, and the I / O A memory area is allocated to the device, and data input / output is executed.

As described above, according to the second embodiment,
The I / O allocation can be changed at any time for operation.

[0061]

According to the present invention, the I / O device is connected to the I / O device.
The I / O memory I / O allocation can be changed and set at any time, so even if the number of words in the connected I / O device changes or the number of I / O devices changes, the changes are made accordingly. Since the input / output allocation can be changed at will, it is not necessary to change the memory design depending on the use of the PC, and the operation efficiency of the PC is improved.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram showing a configuration of a programmable controller according to the first embodiment.

3A is a diagram showing a data configuration of a flag register unit, FIG. 3B is a data configuration of a memory condition setting unit, and FIG. 3C is a diagram showing a data configuration of a data table unit.

FIG. 4 is a block diagram showing a configuration of a programmable controller according to a second embodiment.

FIG. 5 is a diagram illustrating setting values arbitrarily input on a display screen.

FIG. 6 is a diagram showing a configuration of a conventional programmable controller.

FIG. 7 is a diagram showing an example of conventional I / O allocation.

FIG. 8 is a diagram showing another example of conventional I / O allocation.

[Explanation of symbols]

 1 digital boundary value setting means 2 digital address setting means 3 digital table generating means 4 digital input / output means 5 analog boundary value setting means 6 analog address setting means 7 analog table generating means 8 analog input / output means

Claims (2)

[Claims] 1. A digital boundary value setting means (1) for setting a boundary value in a memory input / output area of data input / output to / from a plurality of digital input / output devices each having a device number; Digital address setting means for setting the start address of the input / output data for the input / output device
(2), the device number of each of the plurality of digital input / output devices, the boundary value set by the digital boundary value setting means (1), and the start address set by the digital address setting means (2) A digital table generating means for generating a digital input / output data allocation table in which the device numbers of the plurality of digital input / output devices correspond to the addresses of the memory input / output area based on
(3) and digital input / output means (4) for inputting / outputting data to / from the plurality of digital input / output devices based on the digital input / output data allocation table generated by the digital table generating means (3) Variable programmable controller with I / O assignment. 2. An analog boundary value setting means for setting a boundary value in a memory input / output area of data input / output to / from an analog input / output device each having a device number.
(5) and analog address setting means (6) for setting the start address of the input / output data for the plurality of analog input / output devices
Based on a device number of each of the plurality of analog input / output devices, a boundary value set by the analog boundary value setting means (5), and a start address set by the analog address setting means (6). An analog table generating means (7) for generating an analog input / output data allocation table in which the device numbers of the plurality of analog input / output devices correspond to the addresses of the memory input / output area, and the analog table generating means (7). And an analog input / output unit (8) for inputting / outputting data to / from the plurality of analog input / output devices based on the analog input / output data allocation table generated by (1).