JPH03171267A - Timing generation circuit - Google Patents

Abstract

PURPOSE:To eliminate ROM and to improve the integrated degree of a circuit by constituting the timing generation circuit through the use of comparison circuits and registers. CONSTITUTION:Counters 13X and 13Y inputting clock signals, registers 16X and 16Y storing plural numerical data as external data, comparison circuits 15X and 15Y comparing the size of the outputs of the counters and selected numerical data in the registers, increments 19X and 19Y changing numerical data selected in the registers in correspondence with a compared result to subsequent data are provided. Then, plural numerics are inputted to the registers. While one numerical value is discriminated to be larger than the count value of the counters in the comparison circuits, the registers output a signal '0'. When it is discriminated to be small, the numerical value which is the second largest is compared with the count value and the registers output a signal '1' during the comparing work. Thus, the generation of a timing signal is attained even if ROM is not used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing generation circuit used in an image processing processor.

[Conventional technology]

The image processing processor inputs data from the image memory, processes the data, and stores the processing results in the output image memory. Such an image processing processor does not take care of the entire screen, but has an assigned area of responsibility. Therefore, a plurality of image processing processors are required to process data constituting one screen.

In addition, timing control is required to input data from the image memory to each image processing processor in the order of the predetermined area in charge, and to sequentially store the data in the output image memory after processing. Needed.

FIG. 3 shows a timing generation circuit used in a conventional image processing processor.

A clock signal 12 is supplied from the outside to an input clock terminal 1l of this timing generation circuit. This clock signal 12 is applied to the X direction counter 13X and the Y direction counter 13X.
The signal is supplied to both direction counters 13Y. The count values 14X, 14Y of these counters 13X, 13Y are given as address information for an X-direction ROM (read-only memory) 31x and a Y-direction ROM 31Y, which are provided correspondingly. These ROM31X, 31Y
The timing for setting the area in charge of each image processing processor was described. Therefore, from the output terminals 22X and 22Y arranged on the output side of these ROMs 3 1 .

[Problem to be solved by the invention]

Such conventional timing generation circuits use ROM, which results in poor integration.

For this reason, it is unsuitable for devices that require many ICs (integrated circuits) to be placed on a substrate. Furthermore, since ROM generates a relatively large amount of heat, there is a possibility that peripheral circuit elements may be adversely affected. Furthermore, since it was difficult to freely change the data written in the ROM, it was not easy to change the timing settings.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing generation circuit that does not use a ROM and can easily change timing settings.

[Means to solve the problem]

In the present invention, (i) a counter that inputs a clock signal, and (ii) numerical data of *number are stored as external data, and a signal "0" or a signal "l" is output depending on which one is selected. (iii) a comparison circuit that compares the output of the counter with selected numerical data in the register;
(iv) The timing generation circuit is provided with an incrementer that inputs the comparison result of the comparison circuit and changes the numerical data selected in the register to the next data according to the result.

That is, in the present invention, a plurality of numerical values are input into a register,
For example, while one number is determined by the comparison circuit to be smaller than the count value of the counter, the register outputs the signal "O", and when it is determined to be larger, the count value is compared with the next largest number. , during this comparison operation, the register is connected to the signal “
1" so that a timing signal can be generated without using a ROM.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to examples.

FIG. 1 shows the timing generation circuit according to an embodiment of the present invention.

A clock signal 12 is supplied from the outside to an input clock terminal 11 of this timing generation circuit. This clock signal 12 is applied to the X direction counter 13X and the Y direction counter 13X.
The signal is supplied to both direction counters 13Y. The counted values 14X, 14Y of these counters 13X, 13Y are calculated by the correspondingly provided X-direction comparison circuit 15X and Y-direction comparison circuit 1.
5Y is supplied to one input terminal of each. Timing description data (numeric data) 17X, 17Y are input to the other input terminals of these comparison circuits 15X, 15Y from correspondingly provided X-direction or Y-direction registers 16X, 16Y. .

Desired data is stored in advance in the X direction or Y direction registers 16X, 16Y from a register file (not shown). Comparison of two @road 15X, 15
Y compares the count values 14X, 14Y with each selected numerical data, and the results of this comparison are 18X, 18Y.
incrementers 19X,
Supply to 19Y. The incrementers 19X, 19Y output control signals 2LX, 21Y for incrementing the numerical data as the comparison contents of the corresponding X-direction or Y-direction registers 16X, 16Y according to the comparison results. From the X direction and Y direction registers 16X and 16Y, respective output terminals 22 are output according to the selected numerical data.
Desired data 23X, 23Y are output for X, 22Y.

In the timing generation circuit having such a structure, it is assumed that there are four registers in the X direction register 16X, and these are represented by registers X0 to X.

It is assumed that numerical data "lO" is stored in register x0 and numerical data "20" is stored in register X1. Also, numerical data “3” is stored in register x2.
0” is stored, and the numerical data “40” is stored in register X3.
” is stored.

The comparison circuit 15X first compares the value of the register XO and the value of the X-direction counter 13X.

The count value 14X of the X direction counter 13X is from "0" to "9"
”, the value of register X0 is larger.

Therefore, in these cases, register X outputs a signal "1". When the count value 14X is "10", it matches the value of the numerical data stored in the register x0. In this case, the comparison result 18X causes the incrementer 19X
is incremented and the next register X1 is selected.

Register X is a signal “0” until this is switched.
Output. The count value 14X of the X direction counter 13X is “
The value increases from "10" to "l9", and then when it reaches "20", it becomes equal to the numerical data "20" stored in register x1. At this point, the incrementer 19X is incremented and the next register X2 is selected. .

Until register x2 is switched, the signal “
1” is output. Count value of X direction counter 13X is 14X
increased from '21' to '29', then '3.0'
Then, the numerical data “30” stored in register X2
At this point, the incrementer 19X is incremented and the next register x3 is selected.

Register x3 will hold the signal “0” until this is switched.
” is output. The counted value 14X of the X-direction counter 13X increases from “3l” to “39”, and then when it reaches “40”, it becomes equal to the numerical data “40” stored in the register X. At this point The incrementer 19X is incremented and selects the first register
The signal output from is the timing signal of the image processing processor.

FIG. 2 shows the areas in charge of the image processing processor on one screen and their timing. Here 1
Areas ASB, . . . , H divided into 0 areas indicate the areas in charge of each processor. Further, the signal indicated by the symbol a in this figure represents a change in the timing pulse signal of the processor, that is, the signal in the X direction output from the register X explained in FIG.

In FIG. 1, the change in the signal in the X direction output from the output terminal 22X has been explained, but the timing generation circuit in FIG.
There is a circuit section configured by the SY direction register 16Y and the incrementer 19Y. Therefore, a timing pulse in the b direction (Y direction) in FIG. 2 is generated in this part. This latter timing pulse is the second
As shown in the figure, if the area in charge of each processor is divided into 10 areas ASB,...H, and is divided into two, it is possible to combine the timing pulses in the X and Y directions. Each processor making up one screen can be identified by the following.

For example, in the area A of a certain processor, the X direction is sign a
from "0" to "IO", and the Y direction has the value of code b from 0 to "15", and in the X direction, the area C in charge of the other processor has the value of code a, "20'. to "30", and the value of code b in the Y direction ranges from "0" to "15".

〔Effect of the invention〕

As described above, in the present invention, the timing generation circuit is constructed using a comparator circuit and a register, so a ROM is not required, and the degree of integration of the circuit can be increased. Furthermore, since no ROM is used, the influence of light and heat on peripheral circuits can be avoided.

Furthermore, in the present invention, a plurality of numerical data are stored in the register as external data, so the output of the input bus can be stored in this, and since it is programmable, the timing can be changed arbitrarily. be.

[Brief explanation of the drawing]

1 and 2 are for explaining one embodiment of the present invention. Of these, FIG. 1 is a block diagram of a timing generation circuit, and FIG. An explanatory diagram showing an example of the timing of
FIG. 3 is a block diagram of a conventional timing generation circuit. 11...Input clock terminal, 13X...X direction counter, 13Y...Y direction counter, 15X...X direction comparison circuit, 15Y... ...Y direction comparison circuit, 16X...X direction register, 16Y...Y direction register, 19 father, 19Y...incrementer, 22X,
22Y... Output terminal, A-H... Area in charge of each processor.

Claims (1)

[Claims] A counter that inputs a clock signal, and stores a plurality of numerical data as external data, and outputs a signal "0" or a signal "" depending on which one is selected.
A register that outputs "1" for timing generation, a comparison circuit that compares the magnitude of the output of the counter and the numerical data selected in the register, and a comparison result of this comparison circuit is inputted, and the result is and an incrementer that changes the numerical data selected in the register to the next data according to the timing generation circuit.