JPS5998544A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

Info

Publication number
JPS5998544A
JPS5998544A JP57206170A JP20617082A JPS5998544A JP S5998544 A JPS5998544 A JP S5998544A JP 57206170 A JP57206170 A JP 57206170A JP 20617082 A JP20617082 A JP 20617082A JP S5998544 A JPS5998544 A JP S5998544A
Authority
JP
Japan
Prior art keywords
pellet
inner lead
recess
lead frame
lead pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57206170A
Other languages
English (en)
Inventor
Hajime Murakami
元 村上
Hideki Kosaka
小坂　秀樹
Masachika Masuda
正親 増田
Tokuji Toida
戸井田　徳次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57206170A priority Critical patent/JPS5998544A/ja
Publication of JPS5998544A publication Critical patent/JPS5998544A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
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  • Physics & Mathematics (AREA)
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は半導体装置およびその製造方法に関するもので
ある。
最近、半導体装置の製造においては、集積度の向上への
！求が非常に強くなってお夛、多ビン化の傾向が進んで
いる。
ところで、従来の半導体装置では、ペレツ）１−取シ付
けるためのリードフレームはコバール’Ｊ７ｔは４ｚア
ロイ尋の材料で作られており、その厚さは通常０．１５
−とかなシ厚いものである。
その結果、リードフレームのインナーリード部をエツチ
ング加工で形成する場合、０．１Ｌｍというリードフレ
ームの厚さのために微細加工が困難となり、位置精度の
良いリードフレームを得ることができなかった。その大
め、ワイヤボンディングの不良が発生し、１九半導体装
置の集積度の向上にとりても１つの障害となりていた。
本発明の目的は、前記従来技術の問題点を解決し、位置
精度が良く、微細化の可能な半導体装置を提供すること
にある。
以下、本発明上図面に示す実施例にしたがって詳細に駅
間する。
第１図（、）〜（ｅ）は本発明による半導体装置の一実
施例の製造過程全順次示す拡大部分断面図、同図（ｆ）
はその完成状態の全体断面図である。
この実施例に卦４で、リードフレーム１は通常のプレス
加工、エツチング加工で製作可能な材料、九トエはコバ
ール、４２アロイ等で作られている。
その厚さは、例えば、プレス加工では０．２５■、エツ
チング加工では０．１５ｗｗｍである。このリードフレ
ームｌのペレット取付領斌には、開口部２が形成されて
いる（第１図（−参照）。
この開口部２の中には、第１図（ｂ）ＶＣ示す如く、た
とえば厚さ０，１〜０．５ｍのガラス−エポキシ材料よ
り力るペレット取付基板３が嵌合されている。
このペレット取付基板３は耐熱性の高いｔｆｆｉ絶縁材
料であれば、ガラス−エポキシ材料の池に、フェノール
樹脂、セラきツク等でもよい。
前記リードフレーム１およびペレット取付基１３の上に
は、厚さ１８μｍのアルミニウム（Ａ４　）蒸着層また
は銅（Ｏｕ）の無電解めっき層の如き導電層４が全面に
形成される（第１図（０）参照）。
この導電層４の所定部分には、たとえばホトエツチング
により、所要のインナーリードパターンが微細配線とし
て形成される。その後、インナーリードパターンの上に
は、ニッケル（Ｎｉ）めりきおよび金（Ａｕ）めっき全
順次形成してなる金属めっき層５が形成される。
次に、第１図（（１）Ｋ示すように、ペレット取付基板
３の中央部には、ペレット収容用の凹部６が座ぐ）によ
って加工される。この凹部６はその中に、シリコン（６
１）よりなるペレット７をたとえば接着剤Ｂの如き適宜
の方１式で取り付けるためのものである。
前記凹部６内に取ル付けられたペレット７のポンディン
グパッドと前記金属めっき層５のインナーリードパター
ンとは、たとえば金線よ）なるワイヤ９でポンディング
され、互いに電気的に接続される。
その後、ペレット７およびペレット取付板３、ワイヤ９
等はたとえばトランスファ成形にょ）レジンモールド型
パッケージｉｏ内に封止され、またリードフレーＪ−１
のアウターリード部には錫（８Ｄ）めっきｔ施こした後
、所要の切断および成形加工が行なわれ、半導体装置と
して完成される。
本実施例によれば、リードフレーム１のインナーリード
部がペレット取付基板３およびリードフレーム１上の１
８　ｐｔｎという薄い導電層４をホトエツチングで微細
加工することにょシインナーリードパターンとして形成
されるので、インナーリード部の位置精度が艮く、ワイ
ヤボンディングを正確に行なうことができ、多ビン化に
よる微細化が可能である。
第２図は本発明の他の１つの実施例を示し、同図（ａ）
、（ｂ）は製造過和Ｋかけるペレット取付基板の拡大断
面図、同図（Ｑ）は完成状態の半導体装置を示す断面図
である。
この実施例においては、ペレットを付基板３ａはたとえ
ばガラス−エポキシ材料の如く、耐熱性の良好なｔ気絶
練性の材料よりなり、その中央には、座ぐシによるペレ
ット収容用の凹部６ａが加工されている。また、ペレッ
ト取付基板３ａの凹部６ａの周囲の上面には、たとえば
厚さ１８μｍの銅箔よシなる導電層４ａが設けられてい
る。
この導電層４ａはたとえばホトエツチングにょシインナ
ーリードパターンが微細配線加工されておシ、またその
上には、ニッケルめりきおよび金めつきよシなる金属め
っき層５ａが設けられている（第２図（ａ）参照）。
前記凹部の中には、ペレッ）７ａがたとえばエポキシ樹
脂系の接着剤８ａにより取り付けられている。また、ペ
レット７ａのボンディングパッドと導電層４＆のインナ
ーリードパターンとはワイヤ９ａによってボンディング
される。
その後、ペレット取付基板３ａＦｉたとえばエポキシ系
の接着剤１１によってリードフレーム１ａの所定取付位
置、九とえは通常のペレット取付用のタブ上に接着され
る。リードフレーム１ａｉｊたとえば通常の部分鋏めっ
きフレーム（厚さ０．２５箇）を用いることができる。
次に、ペレット取付板３への導電層４ａのインナーリー
ドパターンとリードフレームｌａの導電部とがワイヤｌ
ｂＫよってボンディングされる。
その後、ペレッ）７ａ、ワイヤ９ａ、９ｂ等はたとえば
エポキシ樹脂によるトランスファ成形でレジンモールド
型パッケージ１０ａ内に封止され、リードフレーム１ａ
のアウターリード部に錫めっきを施して切断および成形
加工を行なうことＫより半導体装置が完成される。
本実診例の場合にも、インナーリード部がペレッ）ＩＲ
付基板３ａ上の１８μｍの薄い導電層４ａのホトエツチ
ングによって微細配線加工されているので、インナーリ
ード部の位置精度が良く、ワイヤボンディング不良を防
止でき、多ピン化による微細化が可能である。
なお、第２図の実施例において、ワイヤ９ａ。
９ｂのボンディングは、ペレット取付基板３ａをリード
フレーム１ａに取り付けた後に連続的に行なってもよい
。
また、本発明は前記実施例に限定される亀のではなく、
りとえば、レジンモールド型パッケージの代シに、レジ
ンボッティング型パッケージを用いること等が可能であ
る。
以上説明したように、本発明によれば、インナーリード
部の位置精度が良好となり、ワイヤポンディング不良を
防止でき、多ピン化による微細化が可能である。
【図面の簡単な説明】
第１図は本発明による半導体装置の一実施例を示し、同
図←）〜（８）はその製造過程を順次示す部分断面図、
（ｆ）は完成状態の断面図、 第２図は本発明の他の実施例を示し、同図（、）と（ｂ
）ｔｄ製造過程の拡大断面図、（０）は完成状態の断面
図である。 １．１ａ・・・リードフレーム、３．３ａ・・・ペレッ
トを付差板、４．４ａ・・・導電層、６．６ａ・・・ペ
レット収容用の凹部、？、７ａ・・・ペレット、９．９
ａ、９ｂ・・・ワイヤ、１０．１０Ｉ！Ｌ・・・レジン
モールド型パッケージ。 第　　１　　図

Claims (1)

  1. 【特許請求の範囲】 １、　　リードフレームの所定位置に嵌合され、ペレッ
    ト収容用の凹部を形成ＬＪｃｔｆｉ絶縁性のペレットを
    何基板を備え、このペレット取付基板のペレット収容用
    の凹部内にをり付けたペレットのポンディングパッドと
    ワイヤボンディングされるインナーリードパターン全前
    記ペレット取付基板およびリードフレームに形成したこ
    とを特徴とする半導体装置。 ２、リードフレームの所定位置に電気絶縁性のペレット
    取付基板を嵌合し、前記リードフレームおよびペレット
    取付基板の上に金属層金膜け、この金属層にインナーリ
    ードパターン會形成した後、前記ペレットを何基板の所
    定位置にペレット収容用の凹部音形成し、この凹部内に
    ペレット奮取〕付ケ、該ペレットのポンディングパッド
    と前記インナーリードパターンとをワイヤボンディング
    すること？Ｉ−特徴とする半導体装置の製造方法。 ３、ペレット収容用の凹部およびインナーリードパター
    ン形成面ケ有する電更絶縁性のペレット取付基板ケ備え
    、このペレット取付基板の前記ペレット収容用の凹部内
    にペレットを取り付け、蚊ペレットのポンディングパッ
    ドと前記インナーリードパターン形成面の所定部とをワ
    イヤボンディングし、かつ前記インナーリードパターン
    形成面の所定部とリードフレームの外部端子への導電部
    と？ワイヤボンディングしてなることを特徴とする半導
    体装置。
JP57206170A 1982-11-26 1982-11-26 半導体装置およびその製造方法 Pending JPS5998544A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57206170A JPS5998544A (ja) 1982-11-26 1982-11-26 半導体装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57206170A JPS5998544A (ja) 1982-11-26 1982-11-26 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
JPS5998544A true JPS5998544A (ja) 1984-06-06

Family

ID=16518962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57206170A Pending JPS5998544A (ja) 1982-11-26 1982-11-26 半導体装置およびその製造方法

Country Status (1)

Country Link
JP (1) JPS5998544A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62112155U (ja) * 1985-12-27 1987-07-17
JPS6422035A (en) * 1987-07-17 1989-01-25 Nec Corp Semiconductor device
DE4313980B4 (de) * 1992-04-28 2005-08-04 Denso Corp., Kariya Integrierte Hybridschaltung und Verfahren zu deren Herstellung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4836983A (ja) * 1971-09-10 1973-05-31
JPS4923203A (ja) * 1972-06-27 1974-03-01
JPS4987539A (ja) * 1972-12-26 1974-08-21

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4836983A (ja) * 1971-09-10 1973-05-31
JPS4923203A (ja) * 1972-06-27 1974-03-01
JPS4987539A (ja) * 1972-12-26 1974-08-21

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62112155U (ja) * 1985-12-27 1987-07-17
JPS6422035A (en) * 1987-07-17 1989-01-25 Nec Corp Semiconductor device
DE4313980B4 (de) * 1992-04-28 2005-08-04 Denso Corp., Kariya Integrierte Hybridschaltung und Verfahren zu deren Herstellung

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