JPS599631A - Manufacture of electrooptic device - Google Patents
Manufacture of electrooptic deviceInfo
- Publication number
- JPS599631A JPS599631A JP57118251A JP11825182A JPS599631A JP S599631 A JPS599631 A JP S599631A JP 57118251 A JP57118251 A JP 57118251A JP 11825182 A JP11825182 A JP 11825182A JP S599631 A JPS599631 A JP S599631A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- insulator
- substrate
- patterned
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1365—Active matrix addressed cells in which the switching element is a two-electrode device
Abstract
Description
【発明の詳細な説明】
２枚の基板により液晶物質を挾持してなる電気光学装置
の少なくとも一方の基板に金属−絶縁体−金属（以下Ｍ
工Ｍ素子という）の構造より成る非線型素子を設置した
電気光学装置のＭＩＭ素子の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION An electro-optical device comprising a liquid crystal material sandwiched between two substrates has a metal-insulator-metal (hereinafter referred to as M
The present invention relates to a method for manufacturing an MIM element for an electro-optical device in which a nonlinear element having a structure called "M element" is installed.
第１図は、Ｍ工Ｍ素子の代表的な形状を示し、第２図は
線ａにおける断面図である。１は基板、２は第１の金属
であり、第１の金属２は、ｈｔ。FIG. 1 shows a typical shape of an M element, and FIG. 2 is a sectional view taken along line a. 1 is a substrate, 2 is a first metal, and the first metal 2 is ht.
Ｔα等の金属で表面が均一に酸化でき、絶縁体となる金
属であればよい。３は第２の金属であり、Ａ Ｌ 、
Ｔ ａ 、 ｒ 、 ｌｉ １ｃ ｒ 等所定の非
線型持性が得られる金属であればよい。４は透明導電膜
であり、ＳｎＯ２、ＩＴＯ等が使用可能である。Any metal such as Tα whose surface can be uniformly oxidized and which serves as an insulator may be used. 3 is the second metal, A L ,
Any metal can be used as long as it can provide a predetermined nonlinearity property, such as T a , r , li 1c r . 4 is a transparent conductive film, and SnO2, ITO, etc. can be used.
５は絶縁体である。5 is an insulator.
従来のＭ工Ｍ素子の製造方法は、第３図に示す如く基板
１上に第１の金属２を形成し、所定の形状にパターニン
グする。次に第４図に示す如く第１の金属２の表面を酸
素ガスを含む高温雰囲気中あるいは陽極酸化等の方法に
より均一に絶縁体５を形成する。次に第５図に示す如く
第２の金属６を形成し、所定の形状にパターニングする
。次に第６図に示す如く透明導電膜４を形成し、所定の
形状にパターニングする。In the conventional manufacturing method of an M element, a first metal 2 is formed on a substrate 1 and patterned into a predetermined shape, as shown in FIG. Next, as shown in FIG. 4, an insulator 5 is uniformly formed on the surface of the first metal 2 in a high temperature atmosphere containing oxygen gas or by a method such as anodic oxidation. Next, as shown in FIG. 5, a second metal 6 is formed and patterned into a predetermined shape. Next, as shown in FIG. 6, a transparent conductive film 4 is formed and patterned into a predetermined shape.
このような製造方法により製造されたＭ工Ｍ素子の代表
的な特性を第７図に示す。縦軸は、Ｍ工Ｍ素子に流れる
電流■であり、横軸はＭ工Ｍ素子の印加電圧Ｖである。FIG. 7 shows typical characteristics of the M element manufactured by such a manufacturing method. The vertical axis is the current (2) flowing through the M element and the horizontal axis is the voltage V applied to the M element.
第７図より明らかなようにＭ工Ｍ素子に印加する電圧■
の向きにより流れる電流値■が異なり、液晶層に直流電
圧が印加されてしまうという欠点があった。液晶物質に
直流電圧を印加すると、液晶物質が劣化するのは公知で
アル。ｔＣ更に、ＭＩＭ素子を製造するためにはバター
ニング工程が３回有り、そのために価格カ高くなってし
まうという欠点があった。また更に３回のパターニング
のために歩留りが悪くなってしまうという欠点があった
。また更に同一ラインに１複数のＭＩＭ素子を設置した
場合隣り合うＭＩＭ素子の配線が表面に絶縁体が形成さ
れた第１の金属となるために、電気光学装置に組立てた
場合、ＭＩＭ素子間の配線が目立ってしまい、電気光学
装置の見栄えが悪くなってしまうという欠点があった。As is clear from Figure 7, the voltage applied to the M element
The current value (2) varies depending on the direction of the liquid crystal layer, which has the disadvantage that a DC voltage is applied to the liquid crystal layer. It is well known that when a DC voltage is applied to a liquid crystal material, the material deteriorates. Furthermore, in order to manufacture an MIM element, a patterning process is required three times, which has the disadvantage of increasing the cost. Furthermore, there was a drawback that the yield was poor due to three patterning steps. Furthermore, when one or more MIM elements are installed on the same line, the wiring of adjacent MIM elements becomes the first metal with an insulator formed on the surface, so when assembled into an electro-optical device, the wiring between the MIM elements This has the disadvantage that the wiring becomes conspicuous and the appearance of the electro-optical device becomes poor.
本発明はかかる欠点を除去したもので、その目的は、２
回のパターニング工程でＭ工Ｍ素子を製造する方法を提
供するものである。The present invention eliminates these drawbacks and has two objectives:
The present invention provides a method for manufacturing an M element using two patterning steps.
以下実施例に基づいて本発明の詳細な説明する。The present invention will be described in detail below based on examples.
第８図から第１８図は本発明の製造方法を示す図である
。第８図に示す様に、基板乙に透明導電膜７と第１の金
属８を所定の膜厚で形成する。次に第４図に示す様に所
定の形状にパターニングし、透明導電膜７および第１の
金属８を同じ形状にエツチングする。8 to 18 are diagrams showing the manufacturing method of the present invention. As shown in FIG. 8, a transparent conductive film 7 and a first metal 8 are formed on a substrate B to a predetermined thickness. Next, as shown in FIG. 4, it is patterned into a predetermined shape, and the transparent conductive film 7 and the first metal 8 are etched into the same shape.
第９図はパターニング形状の一例である。次に第１１図
に示すように、第１の金属８を所定の厚さに形成する。FIG. 9 is an example of a patterning shape. Next, as shown in FIG. 11, the first metal 8 is formed to a predetermined thickness.
次に第１２図に示すように第１の金属８の表面を所定の
厚さだけ酸化し絶縁体９を形成する。この時斜線部で示
す部分は完全に酸化される様に、第１の金属８の厚さあ
るいは絶縁体９の厚さを調整する。次に第１３図に示す
様に第２の金属１０を所定の厚さに形成する。次に第１
５図に示す様に所定の形状に第２の金属１ｏをパターニ
ングする。第１４図斜線部は第２の金属１゜のパターン
形状の一例である。次に第１６図に示す様にパターニン
グした第２の金属１ｏをマスクとし、絶縁体９及び第１
の金属８を除去する。すなわち第１４図の斜線線以外の
絶縁体９及び第１の金属８は除去される。Next, as shown in FIG. 12, the surface of the first metal 8 is oxidized to a predetermined thickness to form an insulator 9. At this time, the thickness of the first metal 8 or the thickness of the insulator 9 is adjusted so that the shaded area is completely oxidized. Next, as shown in FIG. 13, a second metal 10 is formed to a predetermined thickness. Then the first
As shown in FIG. 5, the second metal 1o is patterned into a predetermined shape. The shaded area in FIG. 14 is an example of a 1° pattern shape of the second metal. Next, as shown in FIG. 16, using the patterned second metal 1o as a mask, the insulator 9 and the first
metal 8 is removed. That is, the insulator 9 and the first metal 8 other than the shaded area in FIG. 14 are removed.
第１７図は第１４図の線Ｃにおける断面図である。以上
の様な方法によりＭ工Ｍ素子を製造すると第１８図の斜
線部の部分１１．１２にＭＩＭ素子が形成できる。FIG. 17 is a sectional view taken along line C in FIG. 14. When manufacturing an M element using the method described above, an MIM element can be formed in the shaded areas 11 and 12 in FIG.
以−Ｆの様に本発明によれば、２回のパターニング工程
ニより、Ｍ工Ｍ素子を形成できるという利点がある。ま
た更に、バターニング工程が２回であるために歩留りが
よくなり価格を低くできるという利点がある。また更に
同一ラインに複数のＭ工Ｍ素子を設置すると、隙り合う
Ｍ工Ｍ素子の配線が透明導電膜となり、電気化学装置の
見栄えがよくなるという利点がある。また更に第１８図
に示す様に同時に１１．１２の部分にＭＩＭ素子が形成
でき１２のＭ工Ｍ素子と１１のＭＩＭ素子は逆極性で直
列に接続されてるために、無極性となり液晶層に直流電
圧が印加されるのを防ぐことができるという利点がある
。As described below, according to the present invention, there is an advantage that an M element with an M process can be formed by two patterning steps. Furthermore, since the buttering process is carried out twice, there is an advantage that the yield can be improved and the price can be lowered. Furthermore, when a plurality of M-type M elements are installed in the same line, the wiring of the M-type M elements that overlap each other becomes a transparent conductive film, which has the advantage that the appearance of the electrochemical device improves. Furthermore, as shown in Fig. 18, MIM elements can be formed at the same time in portions 11 and 12, and since M elements 12 and 11 are connected in series with opposite polarities, they become non-polar and form a liquid crystal layer. This has the advantage that direct voltage can be prevented from being applied.
本発明はＭＩＭ素子を設置した電気光学装置を安価に歩
留りよく製造する方法として特に有効なものである。The present invention is particularly effective as a method for manufacturing an electro-optical device equipped with an MIM element at low cost and with high yield.
第１図はＭ工Ｍ素子の代表的な形状であり、第２図は線
ａでの断面図である。
第３図から第６図までは従来の製造方法を示す。
第７図はＭ工Ｍ素子の代表的な特性であり横軸はＭ工Ｍ
素子の印加電圧Ｖであり、騙軸はＭ工Ｍ素子に流れる電
流工である。
第８図から第１８図は本発明によるＭＩＭ素子の製造方
法を示し、第１０図から第１６図および第１７図は第９
図の線すにおけ〕る断面図であり、第１５図、第１６図
は第１４図の線Ｃにおける断面図である。
１．６・・・・・・基板
２．８・・・・・第１の金属
３．１０・・・・・・第２の金属
４．７・・・・・透明導電膜
５．９・・・・・絶縁体
以 上
出願人 株式会社諏訪精工舎
代理人 弁理士 最上 務
第１図
第２Ｖ２１
ず”１′イ ３ トネｌ
第 ４１ソ１
．２５
第５ ！）〈ｊ
第 ６１ツー
第７ ［１”！
第 ８ １”ｉ＜Ｉ
第９図
Ｒ゛
；ｔ’−； ｉ ０ｉ
第１１ｉ”１
第１２図
一′Ｓ１３図
第１Ｌｌ−図
第１５図
第１６図
／／３
１７４−
第１８図FIG. 1 shows a typical shape of an M-work M element, and FIG. 2 is a cross-sectional view taken along line a. 3 to 6 show a conventional manufacturing method. Figure 7 shows the typical characteristics of the M element.The horizontal axis is the M element.
It is the applied voltage V of the element, and the false axis is the current flowing through the M element. 8 to 18 show the method for manufacturing an MIM element according to the present invention, and FIGS. 10 to 16 and 17 show
FIG. 15 and FIG. 16 are cross-sectional views taken along line C in FIG. 14. 1.6...Substrate 2.8...First metal 3.10...Second metal 4.7...Transparent conductive film 5.9.・・・Insulators and above Applicant Suwa Seikosha Co., Ltd. Agent Patent Attorney Mogami Affairs Figure 1 Figure 2V21 7 [1”! 8 1"i<I Fig. 9 R゛;t'-; i 0i 11i"1 Fig. 12-1'S13 Fig. 1Ll-Fig.
Claims (1)
の少なくとも一方の基板に金属−絶縁体−金属の構造よ
り成る非線型特性を有する素子を設置した電気光学装置
の製造方法で、第１の金属２を基板１Ｆに形成し、前記
第１の金属２を所定の形状にパターニングし、前記パタ
ーニングされた第１の金属２の表面を酸化して絶縁体５
を形成し、第２の金属６を前記基板１上に形成し、前記
第２の金属６を所定の形状にパターニングし、前記基板
１１−に透明導電膜４を形成し、前記透明導電膜４を所
定の形状にバターニングして金属−絶縁体−金属の構造
より成る非線型素子の製造方法において、基板６−１１
に透明導電膜７を形成し、前記透明導電膜７」−に第１
の金属８を形成し、前記透明導電膜７および前記第１の
金Ｍ８を同時に所定の形状にバターニングし、前記基板
６上に前記第１の金ｊｇ８を所定の膜厚で形成し、前記
第１の金属８の表面を酸化して絶縁体９を形成し、前記
基板６上に＠２の金属１０を形成し、前記第２の金属１
０を所定の形状にバターニングし、前記第２の金属１０
のバターニング形状をマスクとして利用して、前記絶縁
体９および前記第１の金属８を除去して金属−絶縁体−
金属の構造を有する非線、型素子を製造することを特徴
とする電気光学装置の製造方法。A method for manufacturing an electro-optical device in which an element having a nonlinear characteristic having a metal-insulator-metal structure is installed on at least one substrate of the electro-optical device in which a liquid crystal material is sandwiched between two substrates, the first method comprising: is formed on the substrate 1F, the first metal 2 is patterned into a predetermined shape, and the surface of the patterned first metal 2 is oxidized to form an insulator 5.
a second metal 6 is formed on the substrate 1, the second metal 6 is patterned into a predetermined shape, a transparent conductive film 4 is formed on the substrate 11-, and the transparent conductive film 4 is formed on the substrate 1-. In the method of manufacturing a nonlinear element having a metal-insulator-metal structure by patterning the substrate into a predetermined shape, the substrate 6-11
A transparent conductive film 7 is formed on the transparent conductive film 7'', and a first layer is formed on the transparent conductive film 7''.
the transparent conductive film 7 and the first gold M8 are simultaneously patterned into a predetermined shape, the first gold jg8 is formed on the substrate 6 to a predetermined thickness, The surface of the first metal 8 is oxidized to form an insulator 9, a metal @2 is formed on the substrate 6, and the second metal 1
0 into a predetermined shape, and the second metal 10
Using the patterned shape as a mask, the insulator 9 and the first metal 8 are removed to form a metal-insulator-
A method for manufacturing an electro-optical device, comprising manufacturing a non-wire type element having a metal structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57118251A JPS599631A (en) | 1982-07-07 | 1982-07-07 | Manufacture of electrooptic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57118251A JPS599631A (en) | 1982-07-07 | 1982-07-07 | Manufacture of electrooptic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS599631A true JPS599631A (en) | 1984-01-19 |
| JPH0437969B2 JPH0437969B2 (en) | 1992-06-23 |
Family
ID=14731978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57118251A Granted JPS599631A (en) | 1982-07-07 | 1982-07-07 | Manufacture of electrooptic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS599631A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61134070A (en) * | 1984-12-05 | 1986-06-21 | Matsushita Electric Ind Co Ltd | Thin film transistor array |
-
1982
- 1982-07-07 JP JP57118251A patent/JPS599631A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61134070A (en) * | 1984-12-05 | 1986-06-21 | Matsushita Electric Ind Co Ltd | Thin film transistor array |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0437969B2 (en) | 1992-06-23 |
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