JPH0352277A - Manufacture of nonlinear element - Google Patents

Manufacture of nonlinear element

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Publication number
JPH0352277A
JPH0352277A JP1188112A JP18811289A JPH0352277A JP H0352277 A JPH0352277 A JP H0352277A JP 1188112 A JP1188112 A JP 1188112A JP 18811289 A JP18811289 A JP 18811289A JP H0352277 A JPH0352277 A JP H0352277A
Authority
JP
Japan
Prior art keywords
insulator
mim
metal
insulating film
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1188112A
Other languages
Japanese (ja)
Inventor
Kazuo Tsuruma
鶴間 和男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP1188112A priority Critical patent/JPH0352277A/en
Publication of JPH0352277A publication Critical patent/JPH0352277A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain an active matrix liquid crystal display device employing MIM elements having high display quality by forming an insulating film on the side face of an insulator after the insulator is formed through anodic oxidation. CONSTITUTION:An under layer metal 6, an insulator 7, an insulating film 9 and a transparent conductor 10 are provided. Here, after the metal 6 is patterned, the insulator 7 is formed through anodic oxidation, and the film 9 is formed on the side face of the insulator. In this case, current-voltage characteristic of the insulator 7 is controlled to reduce irregularity of the current- voltage characteristic between MIM(Metal Insulator Meter) elements due to the irregularity of the etching shape on the side face of the metal 6. Thus, an active matrix liquid crystal display device employing MIM element having high display quality can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、アクティブマトリックス方式液晶表示装置に
おいて液晶スイッチング素子に用いられる下層金属一絶
縁体一上層金属構造、あるいは下層金属一絶縁体一透明
導電体構造(以下この2つの構造をMIMと記す)を有
する非線形素子の構造に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a lower metal-insulator-upper metal structure, or a lower metal-insulator-transparent conductive structure used in a liquid crystal switching element in an active matrix liquid crystal display device. The present invention relates to the structure of a nonlinear element having a physical structure (hereinafter these two structures will be referred to as MIM).

〔従来の技術〕[Conventional technology]

MIM素子とは、例えばTa一陽極酸化膜(Tag’s
)一酸化インジウムスズ(ITO)のよ5 ft下層金
属一絶縁体一透明導電体の3層構造であり、Ta−Ta
.05−ITO構造のMIM素子を液晶表示装置に使用
する場合、第6図を用いて説明するよう々工程により製
造することができる。
A MIM element is, for example, a Ta-anodized film (Tag's
) It has a three-layer structure of indium tin monoxide (ITO), a lower metal layer, an insulator, and a transparent conductor.
.. When the MIM element having the 05-ITO structure is used in a liquid crystal display device, it can be manufactured through the steps described with reference to FIG.

第6図(a)はMIM素子を示す平面図であり、第6図
(b)は、第6図(a)におげるC−D線での断面図で
ある。ガラス基板1上にTa2をスパッタリング法によ
り形或し、ノオトエッチングによりパターニングし,T
a2からなるMIM素子の下部電極と配線とを形或する
。このTa2の平面パターン形状は、第6図(a)の実
線11で示す。次に陽極酸化法によりTa2表面に絶縁
体6として’ra,o.を形或する。次に透明導電体4
として、ITOをスパッタリング法により形威し、フォ
トエッチングによりパターニングし、ITOからなるM
IM素子の上部電極と液晶駆動用画素電極とを形戒する
。この透明導電体4の平面パターン形状は第6図(a)
の破線12で示す。Ta2と透明導電体4のクロス部が
MIM素子となる。
FIG. 6(a) is a plan view showing the MIM element, and FIG. 6(b) is a sectional view taken along line CD in FIG. 6(a). Ta2 is formed on the glass substrate 1 by sputtering or patterned by etching.
The lower electrode and wiring of the MIM element consisting of a2 are formed. The planar pattern shape of Ta2 is shown by the solid line 11 in FIG. 6(a). Next, an insulator 6 was formed on the Ta2 surface by anodic oxidation. form. Next, transparent conductor 4
As a result, ITO is shaped by sputtering and patterned by photoetching to form an M made of ITO.
The shape of the upper electrode of the IM element and the pixel electrode for driving the liquid crystal is determined. The planar pattern shape of this transparent conductor 4 is shown in FIG. 6(a).
This is indicated by a broken line 12. The cross section between Ta2 and the transparent conductor 4 becomes an MIM element.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第7図は、従来方法により同一基板上に製作したMIM
素子100[個〕の電流一電圧特性を示したグラフであ
り、電圧を示す横軸の極性は、下部電極Taの極性に対
応する。Taを負極にした場合の各素子間における電流
一電圧特性の矢印15で示すバラツキ(最大値と最小値
に囲まれる範囲)が著しく大きくなる。これは、Ta側
面のエッチング断面の再現性、安定性が通常の膜表面に
比較し、極めて悪いために、側面での電流一電圧特性の
バラツキが、素子全体の電流一電圧特性に影響している
ことが原因である。
Figure 7 shows the MIM fabricated on the same substrate using the conventional method.
It is a graph showing current-voltage characteristics of 100 elements, and the polarity of the horizontal axis indicating voltage corresponds to the polarity of the lower electrode Ta. When Ta is used as the negative electrode, the variation (range surrounded by the maximum value and minimum value) shown by the arrow 15 in the current-voltage characteristics between each element becomes significantly large. This is because the reproducibility and stability of the etched cross section on the Ta side surface is extremely poor compared to the normal film surface, so variations in current-voltage characteristics on the side surface affect the current-voltage characteristics of the entire device. The reason is that there is.

本発明は、この様な課題を解決したもので、表示品質の
高い、MIM素子を用いたアクティブマトリクス液晶表
示装置の製造方法を提供することを目的とする。
The present invention has solved these problems, and an object of the present invention is to provide a method for manufacturing an active matrix liquid crystal display device using MIM elements with high display quality.

〔課題を解決するための手段〕 本発明はMIM素子において、下層金属のバターニング
後に、陽極酸化法により絶縁体を形或後、次にこの絶縁
体側面に絶縁膜を形成することにより、絶縁体の電流一
電圧特性を支配的にして、下層金属の側面のエッチング
形状のバラツキによる、MIM素子間の電流一電圧特性
のバラツキを減少させるものである。
[Means for Solving the Problems] In an MIM element, the present invention forms an insulator by an anodic oxidation method after patterning a lower metal layer, and then forms an insulating film on the side surface of the insulator. By making the current-voltage characteristics of the MIM element dominant, variations in the current-voltage characteristics between MIM elements due to variations in the etching shape of the side surfaces of the underlying metal are reduced.

〔実施例〕〔Example〕

以下、本発明の詳細を実施例に基づいて説明する。 Hereinafter, details of the present invention will be explained based on examples.

(実施例1) 第2図は、本実施例により製作したMIM素子を示す平
面図であり、第1図(a)〜(e)は第2図のA−B断
面を示す工程断面図である。以下第1図と第2図とを交
互に参照して説明する。
(Example 1) FIG. 2 is a plan view showing the MIM device manufactured according to this example, and FIGS. 1(a) to (e) are process cross-sectional views showing the A-B cross section in FIG. be. The following description will be given with reference to FIG. 1 and FIG. 2 alternately.

まず第1図(a)に示すように、ガラス基板5上に下層
金属6としてTaをスパッタリング法により厚さ200
(nm)形或する。これを通常のフォトエッチングによ
りバターニングする。この下層金属6の平面パターン形
状は第2図の実線16で示す。
First, as shown in FIG. 1(a), Ta was deposited on a glass substrate 5 as a lower metal layer 6 to a thickness of 200 mm by sputtering.
(nm) shape. This is buttered by normal photo-etching. The planar pattern shape of the lower metal layer 6 is shown by a solid line 16 in FIG.

次に第1図(b)に示すように、クエン酸0.1〔%〕
水溶液中で30(V)の電圧で下層金属6であるTaを
陽極酸化し、下層金属−6の表面に絶縁体7としてTa
,0,を厚さ5 0 [ n m ]形或する。
Next, as shown in Figure 1(b), citric acid 0.1 [%]
Ta, which is the lower layer metal 6, is anodized at a voltage of 30 (V) in an aqueous solution, and the Ta which is the insulator 7 is applied to the surface of the lower layer metal 6.
,0, with a thickness of 50 [nm].

次に第1図(C)に示すように、全面にレジスト8を塗
布しガラス基板5の裏面から全面露光するバック露光に
より、絶縁体7の上面にレジスト8を形或してから、プ
ラズマCVD法により全面に絶縁膜9としてSiNxを
厚さ2 0 0 ( n m ]形成する。
Next, as shown in FIG. 1(C), a resist 8 is applied to the entire surface, and the resist 8 is formed on the upper surface of the insulator 7 by back exposure in which the entire surface is exposed from the back surface of the glass substrate 5, and then plasma CVD is applied. An insulating film 9 of SiNx is formed to a thickness of 200 nm over the entire surface by a method.

次に第1図(d)に示すように、レジスト8を除去する
ことによりこのレジスト8上面の絶縁膜9を同時に除去
するリフトオフ法により、レジスト8上の絶縁膜9を剥
離する。
Next, as shown in FIG. 1(d), the insulating film 9 on the resist 8 is peeled off by a lift-off method in which when the resist 8 is removed, the insulating film 9 on the upper surface of the resist 8 is simultaneously removed.

次に第1図(e)に示すように、透明導電体10として
例えばITOをスパッタリング法で厚さ2 0 0 [
 n m )形成し、通常のフォトエッチングにより透
明導電体10をパターニングする。この透明導電体10
の平面パターン形状は第2図の破線14で示す。
Next, as shown in FIG. 1(e), as a transparent conductor 10, for example, ITO is sputtered to a thickness of 200 [
nm) is formed, and the transparent conductor 10 is patterned by ordinary photoetching. This transparent conductor 10
The planar pattern shape of is shown by the broken line 14 in FIG.

尚、製作したMIM素子部の面積は16〔μM〕とした
Note that the area of the manufactured MIM element portion was 16 [μM].

第3図は同一基板上に製作したMIM素子100〔個〕
の電圧一電流特性を示したものである。従来法による第
7図と比較し、Ta負極時の矢印16で示すMIM素子
間の特性バラッキが減少している。
Figure 3 shows 100 MIM elements fabricated on the same substrate.
This shows the voltage-current characteristics of . Compared to the conventional method shown in FIG. 7, the variation in characteristics among MIM elements shown by the arrow 16 when Ta negative electrode is used is reduced.

(実施例2) 本発明における第2の実施例を第4図(a)〜(e)を
用いて説明する。
(Example 2) A second example of the present invention will be described using FIGS. 4(a) to (e).

第4図(a)、(b)に示すように、実施例lと同様に
ガラス基板5上の下層金属6表面に絶縁体7を形成する
。次に第4図(C)に示すように絶縁膜9としてプラズ
マCVD法により全面にSiNxを厚さ2 0 0 (
 n m )形或する。次に第4図(d)に示すように
、この絶縁膜9をリアクティブイオンエッチング(RI
E)I/cよりエッチバグクする。一こノのRIEにお
いては下層金R6の側面が陰となりイオンが到達せず側
面部に絶縁膜9がエッチングされずに残る。次に第4図
(e)に示すように、透明導電体10を形或することに
より実施例1と同様の結果が得られる。
As shown in FIGS. 4(a) and 4(b), an insulator 7 is formed on the surface of the lower metal 6 on the glass substrate 5 in the same manner as in Example 1. Next, as shown in FIG. 4(C), as an insulating film 9, SiNx is deposited over the entire surface to a thickness of 200 (
n m ) form. Next, as shown in FIG. 4(d), this insulating film 9 is subjected to reactive ion etching (RI).
E) Ecchibug from I/c. In this RIE, the side surfaces of the lower gold layer R6 become negative and ions do not reach them, so that the insulating film 9 remains on the side surfaces without being etched. Next, as shown in FIG. 4(e), the same results as in Example 1 can be obtained by shaping the transparent conductor 10.

(実施例3) 本発明における第3の実施例を第5図(a)〜(e)を
用いて説明する。
(Example 3) A third example of the present invention will be described using FIGS. 5(a) to (e).

第5図(a), (b)に示すように、実施例lと同様
にガラス基板5上の下層金属6表面に絶縁体7を形成す
る。次に第5図(C)に示すように絶縁膜9としてプラ
ズマCVD法により全面にS iNxを厚さ300Cn
m)形或し、さらにその上にレジスト8を全面に厚さ5
 0 0 ( n m )形成する。レジスト8は段差
を緩和する作用があり、レジスト8表面はほぼ平坦にな
る。
As shown in FIGS. 5(a) and 5(b), an insulator 7 is formed on the surface of the lower metal 6 on the glass substrate 5 in the same manner as in Example 1. Next, as shown in FIG. 5(C), SiNx is deposited to a thickness of 300 Cn over the entire surface by plasma CVD as an insulating film 9.
m) shape, and then apply resist 8 to a thickness of 5 over the entire surface.
00 (nm) is formed. The resist 8 has the effect of alleviating the difference in level, and the surface of the resist 8 becomes substantially flat.

次に第5図(d)に示すように、絶縁膜9とレジスト8
とが同一のエッチング速度となる条件でRIEt,、絶
縁体7が出るところまでレジスト8と絶縁膜9とをエッ
チングする。その後第5図(e)に示すように透明導電
体10を形或することにより実施例1と同様の結果が得
られる。
Next, as shown in FIG. 5(d), the insulating film 9 and the resist 8
The resist 8 and the insulating film 9 are etched under conditions such that the etching rate is the same as that of the resist 8 and the insulating film 9 until the insulator 7 is exposed. Thereafter, the same results as in Example 1 can be obtained by shaping the transparent conductor 10 as shown in FIG. 5(e).

〔発明の効果〕〔Effect of the invention〕

以上の説明の如く、MIM素子形或プロセスにおいて陽
極酸化による絶縁体形或後に、絶縁体の側面に絶縁膜を
形戒することにより、下層金属上面の絶縁体のみが、素
子の電流一電圧特性に支配的となるため、電気特性の均
一化が達或でき、表示品質の高いMIM素子を用いたア
クティブマトリクス液晶表示装置が得られる。またその
効果は、金属一絶縁体一透明導電体構造以外の金属一絶
縁体一金属構造のMIM素子においても同様に得られる
As explained above, by forming an insulator by anodic oxidation in the MIM device or process, and then forming an insulating film on the side surface of the insulator, only the insulator on the upper surface of the lower metal can affect the current-voltage characteristics of the device. Since this is dominant, it is possible to achieve uniform electrical characteristics and to obtain an active matrix liquid crystal display device using an MIM element with high display quality. Further, the same effect can be obtained in an MIM element having a metal-insulator-metal structure other than the metal-insulator-transparent conductor structure.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(e)は本発明の第1の実施例における
非線形素子の製造方法を工程順に示す断面図、第2図は
本発明における非線形素子の製造方法を説明する平面図
、第3図は本発明による非線形素子の電流一電圧特性を
示すグラフ、第4図(al〜(e)は本発明の第2の実
施例における非線形素子の製造方法を工程順に示す断面
図、第5図(a)〜(elは本発明の第3の実施例にお
ける非線形素子の製造方法を工程順に示す断面図、第6
図は従来のTa一Ta205−ITO構造のMIM素子
を示し、第6図(a)は平面図、第6図(b)は製造方
法を説明するための断面図、第7図は従来のTa  T
a205−I To構造のMIM素子の電流一電圧特性
を示すグラフである。 6・・・・・・下層金属、 7・・・・・・絶縁体、 9・・・・・・絶縁膜、 10・・・・・・透明導電体。 第1図 第4図 第5図 第6図 (b) ム
1(a) to (e) are cross-sectional views showing the method for manufacturing a nonlinear element according to the first embodiment of the present invention in order of steps; FIG. 2 is a plan view illustrating the method for manufacturing a nonlinear element according to the present invention; FIG. 3 is a graph showing the current-voltage characteristics of the nonlinear element according to the present invention, FIGS. 5(a) to (el are cross-sectional views showing the manufacturing method of a nonlinear element according to the third embodiment of the present invention in order of steps;
The figures show a conventional Ta-Ta205-ITO structure MIM element, FIG. 6(a) is a plan view, FIG. 6(b) is a cross-sectional view for explaining the manufacturing method, and FIG. 7 is a conventional Ta-Ta205-ITO structure MIM element. T
It is a graph showing current-voltage characteristics of an MIM element having a205-I To structure. 6... Lower layer metal, 7... Insulator, 9... Insulating film, 10... Transparent conductor. Figure 1 Figure 4 Figure 5 Figure 6 (b)

Claims (1)

【特許請求の範囲】[Claims] 下層金属上に陽極酸化により絶縁体を設け、さらに該絶
縁体上に上層金属あるいは透明導電体を設けてなる非線
形素子の製造方法において、前記下層金属上に陽極酸化
法により前記絶縁体を形成し、次に前記絶縁体の側面に
絶縁膜を形成することを特徴とする非線形素子の製造方
法。
In a method for manufacturing a nonlinear element in which an insulator is provided on a lower metal layer by anodizing, and an upper metal layer or a transparent conductor is further provided on the insulator, the insulator is formed on the lower metal layer by an anodizing method. . A method of manufacturing a nonlinear element, comprising: next forming an insulating film on a side surface of the insulator.
JP1188112A 1989-07-20 1989-07-20 Manufacture of nonlinear element Pending JPH0352277A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1188112A JPH0352277A (en) 1989-07-20 1989-07-20 Manufacture of nonlinear element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1188112A JPH0352277A (en) 1989-07-20 1989-07-20 Manufacture of nonlinear element

Publications (1)

Publication Number Publication Date
JPH0352277A true JPH0352277A (en) 1991-03-06

Family

ID=16217913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1188112A Pending JPH0352277A (en) 1989-07-20 1989-07-20 Manufacture of nonlinear element

Country Status (1)

Country Link
JP (1) JPH0352277A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568289A (en) * 1994-03-18 1996-10-22 Sharp Kabushiki Kaisha Liquid crystal display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568289A (en) * 1994-03-18 1996-10-22 Sharp Kabushiki Kaisha Liquid crystal display device

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