JPH02244126A - Production of thin-film transistor panel - Google Patents

Abstract

PURPOSE:To prevent the generation of the dielectric breakdown between bus lines during the course of a production process by removing two sets of connecting lines in the final state of panel formation and disconnecting connecting terminals from the terminal parts of gate bus lines and the terminal parts of drain bus lines. CONSTITUTION:The gate bus lines GB and the drain bus lines DB are respectively commonly connected over the entire part and further the terminal parts DT of the gate bus lines GB and the drain bus lines DB are drawn out and are formed into the structure that these parts overlap on top and bottom. The overlapped parts are irradiated with a laser beam to connect two sets of the bus lines. The production process is progressed in this state and the gate bus lines GB and the drain bus lines DB as well as the respective bus lines are separated from each other in the final etching stage. The dielectric breakdown between the two bus lines by static electricity, etc., and further, the dielectric breakdown between the gates and drains connected thereto are prevented.

Description

[Detailed Description of the Invention] [Summary] With regard to a method for manufacturing a thin film transistor panel, the present invention aims to prevent dielectric breakdown between pass lines during the manufacturing process without complicating the manufacturing process. In a method for manufacturing a thin film transistor panel in which a gate bus line that commonly connects electrodes and a drain bus line that commonly connects drain electrodes of the same transistor are provided, in the step of forming the gate bus line, each gate The terminal portion of the gate bus line extending from one end of the bus line is short-circuited by a connecting wire, and a connecting terminal is led out from the terminal portion of the shorted gate bus line. The extended drain bus line terminal portion is short-circuited by a connecting wire, and a connecting terminal is led out from this shorted drain bus line terminal portion and superimposed on the connecting terminal led out from the gate bus line terminal portion, and the superimposed two In the final step of forming the panel, the two sets of connection wires are removed and the connection terminals are connected to the gate bus line terminal section. and the drain bus line terminal section.

[Industrial application field]

The present invention relates to a method for manufacturing a thin film transistor panel.

Many pixels arranged in a matrix on an insulating substrate,
Active matrix liquid crystal display devices, which are each driven by thin film transistors, are being actively developed in various fields because they are thin and can produce high-quality, full-color images. To make this truly practical,
Challenges include further simplifying the manufacturing process and improving the breakdown voltage between the TFT section and the pass line.

[Conventional technology]

In a thin film transistor panel in which a large number of pixel electrodes arranged in a matrix, a plurality of thin film transistors associated with each pixel electrode, and pass lines of rows and columns paired with windows are formed on two insulating substrates, The two sets of pass lines intersect on the same substrate.

For insulation between pass lines that overlap vertically at this intersection,
There are those that use an insulating film such as a gate insulating film that is normally used in the structure of a thin film transistor matrix, and those that use an insulating film between the eyebrows.

Of these, the former method, in which the insulating film normally used to configure thin film transistors is also used for insulating between pass lines, simplifies the manufacturing process because it does not require a special process to form an insulating film between the eyebrows. It has the advantage of being A method of manufacturing a thin film transistor panel using this method will be explained below with reference to FIGS. 3(a) to 3(e).

[See FIGS. 3(a) and (f)] A gate electrode material film such as a Ti film 2 is formed on a transparent insulating substrate 1, and this is etched into a predetermined pattern to form gate electrodes G and A gate bus line CB is formed.

Next, gate insulating film (SiNx film)3. An active semiconductor layer (a-3i layer) 4° and a protective film (Stow film) 5 are formed.

[See figures (b) and (g)]

After applying the resist, back exposure using the gate electrode G as a mask and mask exposure using a photomask are performed to form a resist film 6 only on the upper part of the gate electrode G. Next, the protective film 5 is etched using the resist film 6 as a mask, and then the contact layer 7 and the metal film (Ti
After forming the film 8, lift-off is performed.

[See figures (C) and (h)]

Next, using a resist film (not shown) for element isolation and drain bus line formation as a mask, the contact layer 7. Metal film 8. Then, unnecessary portions of the active semiconductor layer 4 are removed to perform element isolation, and source and drain electrodes S and D and a drain bus line DB are formed.

[See (d) and (i) in the same figure.] After removing the above resist film, a resist film (not shown) for forming a pixel electrode is formed again, and a conductive film such as an ITO film is formed. , lift-off is performed using the resist film to form a pixel electrode E.

(See figure (e)) After this, a resist film (not shown) is further formed to expose only the terminal part GT of the gate bus line, and using this as a mask, the Ti film 8 and the contact layer 7 are removed. The terminal part GT of the gate bus line is exposed. Since the drain bus line terminal portion DT is formed with its surface exposed during pattern formation, there is no need for a particular step of exposing it.

In the above manufacturing method, the plurality of gate bus lines CB and drain bus lines DB are separated from each other, and the gate bus lines GB and drain bus line terminal portions are also not connected. Therefore, each pass line, gate, source, and drain electrodes are easily charged, and therefore there is a problem in that dielectric breakdown is easily caused at the TFT section or the intersection of the pass lines.

[Problem to be solved by the invention]

Therefore, attempts have been made for some time to connect each pass line to each other and to connect two sets of pass lines to prevent dielectric breakdown during the process, but this inevitably complicates the manufacturing process. There has been a strong desire for a production method that can be put to practical use.

An object of the present invention is to prevent dielectric breakdown between pass lines during the manufacturing process without complicating the manufacturing process.

[Means to solve the problem]

The present invention will be explained in detail with reference to FIG.

As shown in the figure, initially, the gate bus line GB and drain bus line DB are connected in common across all lines, and then the terminal portions of the gate bus line and drain bus line are pulled out to form a vertically overlapping structure. . By irradiating this overlapping portion with a laser beam, the two sets of pass lines are connected.

Proceed with the manufacturing process in this state, and in the final etch process,
Gate bus lines CB and drain bus lines DB are isolated from each other and between each pass line.

[For production]

According to the present invention, a plurality of gate bus lines GB and drain bus lines DB are connected in common, and these two sets of pass lines are also connected to have a common potential. dielectric breakdown between pass lines,
Furthermore, dielectric breakdown between the gate and drain connected thereto can be prevented.

Furthermore, when implementing the present invention, there is no need to increase the number of masks used.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 2(a) to 2(e). FIGS. q) is a plan view of the main part of one pixel area, and the cross-sections taken along line A-A are shown in (f) to (n
).

[See FIGS. 2(a), (f), (1)] On the transparent insulating substrate 1, as the gate electrode material film 2, a Ti film 21 with a thickness of about 1000 mm and an Al film 22 with a thickness of about 1,000 cm are formed. The film is deposited to a thickness of 1,000 people. Next, this Ti film 21 and Al film 2
2 is masked with a resist film (not shown) and etched to form a gate electrode G and a gate bus line CB. At this time, a connection line 31 is provided in the gate bus line terminal part GT to connect the pass lines with each other, and a lead line 32 is led out from the gate bus line terminal part GT, and a connection terminal T1 is provided at the tip thereof.

The connection line 31 and the lead line 32 have a width of about 5 to IO μm, which is extremely thin compared to the width of the gate bus line CB and the gate bus line end portion GT. Further, the connection terminal T1 is a terminal for laser connection, which will be described later.

[See figures (b), (g), and fig.]

Next, side etching is performed on the Affi film 22 using an isotropic wet etching method or a dry etching method. As a result, the Al film 22 on the narrow gate electrode G, on the connection line 31 of the gate bus line terminal part GT, and on the lead line 32 is removed. Therefore, the Al film 22
remains only on the wide gate bus line CB and the gate bus line end portion GT.

[See (c) and (n) in the same figure]

After removing the resist film, Si
The Nx film 3 is approximately 3000 μm thick, the a-3i layer 4 as an active semiconductor layer is approximately 200 to 1000 μm thick, and the SiO□ film 5 as a protective film is approximately 1000 to 2000 μm thick. Form a film.

[See (i) and (0) in the same figure] Next, after applying resist, back exposure and mask exposure are performed.
A resist film 6 is formed only above the gate electrode G. Next, the Stow film 5 is etched using the resist film 6 as a mask. Subsequently, n” as a contact layer.
The thickness of the a-St layer 7 is approximately 300 to 500 mm, and the Ti film 8 is approximately 1000 to 200 mm thick as the metal film of the drain/source electrode material.
The film is deposited to a thickness of 1,000 people. After that, lift-off is performed, and the resist film 6 and the n''a-3i layer thereon and the T
Remove the i-film.

[See Figures (c), (j), and (p) 1. Next, the Ti film is removed using the resist film (not shown) as a mask. n
"a-b 3i Unnecessary portions of the layer 4 are removed to form a source electrode S, a drain electrode, and a drain bus line DB. At this time, all lines are connected to a common connection line 33 at the drain bus line terminal part DT. Connect this connection wire 3 to
Connect the connecting terminal T2 connected to the extension part of No. 3 to the above connecting terminal T.
Place it on l.

Next, after peeling off the resist film used as the mask, a laser beam is irradiated onto the overlapping portion of the connection terminals TI and T2 to electrically connect the upper and lower films. As a result, the gate bus line CB and the drain bus line DB are brought into conduction with each other.

[See (9) and (q) of the same figure] Next, a resist film (not shown) is formed to cover the area other than the pixel electrode forming area, and the ITO film 9 is formed as a transparent conductive film to a thickness of about 1,000 to 2,000 mm. Then, the resist film is removed and the ITOWA deposited thereon is lifted off to form the pixel electrode E.

In this step, the end of the pixel electrode E is overlapped with the end of the source electrode S to connect them.

[See figure (d)] Next, as shown by dotted hatching, a resist film 10 is formed to cover the display area. The portion not covered with this resist film 10 is an extension of the gate insulating film S.
iN. covered with a membrane.

[See figure (e)]

Therefore, etching is performed using the resist film 10 as a mask to remove the extended portion of the gate insulating film 3 and expose the gate bus line terminal portion GT and drain bus line terminal portion DT.

Next, etching is performed using the resist film 10 and the A2 film 22 on the gate bus line end portion GT as a mask. As a result, all the exposed surface portions of the Ti film 21 are removed, but A! The portion covered with membrane 22 remains.

After this, the Affi film 22 used as the mask is removed, and finally the resist film 10 is removed.

As shown above, the gate bus line terminal section GT and the drain bus line terminal section DT can be separated one by one.

In this embodiment described above, a large number of gate bus lines GB
The drain bus lines DB are connected to each other and to the drain bus lines DB when forming the pass lines, and the connection terminals TI and T2 are also connected between both pass lines by laser irradiation.The manufacturing process is continued in this state, and in the final process. Separate each part.

Therefore, even if charging occurs during the manufacturing process, all the pass lines and the electrodes connected to the pass lines are all kept at the same potential, so no dielectric breakdown occurs.

Therefore, short-circuit defects of many elements and pass line intersections do not occur, and reliability and manufacturing yield are improved. Moreover, since the gate bus line GB is a laminated film of the Ti film 21 and the A2 film 22, the resistance of the pass line can be reduced.

[Effects of the Invention] As explained above, according to the present invention, a highly reliable thin film transistor panel can be manufactured at a high yield without increasing the number of masks.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIGS. 2(a) to (b) are detailed explanatory diagrams of the present invention, and FIGS. 3(a) to (i) are explanatory diagrams of a conventional thin film transistor manufacturing method. . In the figure, 1 is an insulating substrate, 3 is a gate insulating film (Si
N, film), 4 is a-3i layer (active semiconductor layer), 6.10
21 is a resist film, 21 is a Ti film, 22 is an Al film, 31 is a connection line, 32 is a lead line, 33 is a connection line, G is a gate electrode, S is a source electrode, D is a drain electrode, CB is a gate bus line, GT is the gate bus line terminal part, DB is the drain bus line, DT is the drain bus line terminal part, T
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Claims (1)

[Claims] A gate bus line GB that commonly connects the gate electrodes (G) of thin film transistors, and a drain bus line (DB) that commonly connects the drain electrodes (D) of the same transistors.
In the method for manufacturing a thin film transistor panel, in the step of forming the gate bus line, a gate bus line terminal portion (GT) extending from one end of each gate bus line (GB) is connected to a connecting line (31). At the same time, this short-circuited gate bus line terminal (
In the step of forming the drain bus line, each drain bus line (T1) is led out from the drain bus line (GT).
Drain bus line terminal section (DB) extended from one end of the drain bus line (DB)
DT) is short-circuited by the connecting wire (33), and the short-circuited drain bus line terminal (DT) is connected to the connecting terminal (
T2) is derived from the gate bus line terminal section (GT).
The final stage of panel formation includes the step of superimposing the superimposed two connection terminals (T1, T2) on the connection terminal (T1) derived from In the process, the two sets of connection wires (3
1, 33), and the connection terminals (T1, 33) are removed.
A method for manufacturing a thin film transistor panel, characterized in that T2) is separated from a gate/bus line terminal portion (GT) and a drain bus line terminal portion (DT).