JPS5993491A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to display devices for teletext broadcasting systems, captain systems, personal computers, television games, and the like.

Configuration of a conventional example and its problems A conventional display device will be explained with reference to FIG. 1st
The figure is a block diagram of a continuous circuit in a conventional display device.
(1) is the dot counter 1. (2) is a memory control output circuit, (3) is a horizontal/vertical synchronization signal and read address generation circuit, (4) is a display memory, (5) is a parallel-to-serial conversion circuit, (6) is a delay-dot variable shift register, (7) is a delay dot number control circuit, and (8) is a display circuit. In this way, conventionally, the phases of the display horizontal synchronizing signal and the display memory read cycle are fixed and read. Therefore, in order to perform horizontal scrolling display, a method is used in which the memory is read out one cycle earlier, the display is delayed by a shift register, and horizontal scrolling is performed. However, such a conventional device requires shift registers capable of controlling the number of delay dots equal to the number of memory planes, and the control thereof is also complicated.

OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned drawbacks of the conventional art, and aims to provide a display device that can omit delay-controllable shift registers, which are required for the number of memory frames, and can simplify the circuit.

Structure of the Invention In order to achieve the above object, the display device of the present invention includes a frequency division counter that divides the frequency of a display dot clock signal, and a memory control output determination device that determines the state of a memory control output according to the output of the division counter. and a display memory successive circuit that stops the branch counter during the horizontal retrace period and synchronizes the phase of the display horizontal synchronization signal and the display memory read cycle in units of dot clocks. .

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a readout circuit in one embodiment of the present invention, and FIG. 3 is a time chart of the circuit shown in FIG. 2. In FIGS. 2 and 8, (a) is a display dot clock, (9) is a frequency division counter that divides the frequency of this signal, and (b) is a signal indicating the division state. 00 is a memory control output determining circuit that generates a signal (C8, etc.) for reading out the display memory Q according to the frequency division state signal (b), and (C) is the memory control signal that is its output. be. θ
υ is a horizontal/vertical synchronizing signal and successive address generation circuit that counts the display dot clock (a) and generates the horizontal/vertical synchronizing signal (d), and at the same time generates the synchronization signal, it outputs the count to generate the memory successive address ( e).

(f) is a horizontal synchronizing signal, aQ is a counter control circuit that stops the branch counter (9) by an arbitrary number of dots at an arbitrary time during the horizontal retrace period, and Q) is a counter control signal for this purpose. The display data (h) read out from the display memory (2) by the memory control signal (c) and memory read address (e) is normally processed by a parallel-serial conversion circuit (
11, becomes the display video signal (i), and is sent to the display circuit a<
is input. Scanning of this display circuit Q4 is controlled by a horizontal and vertical synchronizing signal (d). Here, in order to match the phase of the display horizontal synchronization signal and the memory read cycle,
The counter control circuit aQ sends an ST double signal to the branch counter (9) during the horizontal retrace period.
) and enlarge the memory control output (represented by (C5) in FIG. 8).

In FIG. 8, (DOT) is the display dot clock;
(Surface) is the horizontal synchronization signal. In this way, the memory read cycle can be shifted by the time specified by the counter stop signal (ST), and the phase relationship between the horizontal synchronizing signal (plane) and the display data can be determined dot by dot.

Also, by outputting this (ST) signal one dot earlier, as shown in Fig. 8 (
By doing as shown in B), data can be displayed one dot to the left (normally scanned from left to right) compared to (A). By repeating this, horizontal scrolling display is possible.

Further, the display memory Q″4 is connected to a central processing unit (CPU).
In a system in which the reading cycle is synchronized with the CPU cycle, by enlarging the CPU clock signal (d) ((j) in Fig. 2) in the same way as the memory control output, Read cycle and CP easily
It is possible to synchronize the U cycle.

As described in detail, according to the present invention, there is no need for delay control heatable shift registers depending on the number of memory planes as in the past, and it is possible to operate multiple memory planes by simply adding a clock control circuit. It is possible to provide an easy-to-use display device that can correspond to the above, simplify the system and reduce the cost, and also easily control the display position depending on the situation and synchronize the display system with the control system using a CPU. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a readout circuit in a conventional display device, FIG. 2 is a block diagram of a readout circuit used in a display device according to an embodiment of the present invention, and FIG. 8 is a timing diagram of the circuit shown in FIG. It is a chart. (9)...Frequency division counter, (10...Memory control output determination circuit, 0υ...Horizontal/vertical synchronization signal and successive address generation circuit, (2)...Display memory, 03...Parallel- Serial conversion circuit, ◇Xu... Display circuit, 0 o'clock... Counter control circuit, (DOT)... Display dot clock, (DSP)... Signal indicating display period, (
JIB)--Horizontal brushing signal, (HD)...
・Horizontal synchronization signal, (ST)... Counter stop signal, (
C5)...Memory control signal, (φ)...CPU clock signal, agent Yoshihiro Morimoto

Claims (1)

[Scope of Claims] 1. A frequency division counter that divides the frequency of a display dot clock signal, and a memory control output determination circuit that determines the state of a memory control output according to the output of this division counter; A display device comprising a display memory read circuit that stops a cycle counter for five horizontal retrace periods to synchronize the phases of a display horizontal synchronizing signal and a display memory read period in units of dot clocks. 2. The display memory readout circuit has a counter control circuit that controls the frequency division counter so that the same output value is output for an arbitrary number of dot clocks at an arbitrary output value of the branch counter during the horizontal retrace period. Claim 1, in which the display screen is horizontally scrolled dot by dot.
Display device as described in section. 3. A control signal for the central processing unit is output, and the phases of the display horizontal synchronization signal, the display memory read cycle, and the operation cycle of the central processing unit are synchronized in dot clock units. display device.