JPS5987866A - Manufacture of bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to manufacture a bipolar transistor to operate at a high speed by a method wherein channeling ion implantation is applied actively to formation of the collector of the bipolar transistor formed according to triple diffusion. CONSTITUTION:After an oxide film 12 is etched to be removed wholly, photo resist patterns 15 are covered on the parts other than the collector region formation programing part, and after the implanting direction of P<+> ions and the <110> crystal axis of a substrate 11 are made to coincide within + or -0.3 deg., P<+> channeling ions are implanted by the dose of 4X10<13>cm<-2>, for example, to the collector region formation programing part. After photo resist patterns 19 to cover the parts other than the base region formation programing part are covered, B<+> ions are implanted by the dose of 1X10<14>cm<-2>, for example. Then after the photo resist patterns 19 are removed, a heat treatment is performed in an N2 atmosphere to form a P type base region 20 of 0.4mum thickness. A part of silicon nitride film 18 and a thermal oxide film 16 corresponding to the upper part of the P type base region 20 are etched selectively in order to be removed to form openings 24, and after an Al-Si film is deposited on the whole surface, patterning is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a bipolar semiconductor device, and particularly to a method for forming a bipolar transistor by triple diffusion.

[Technical background of the invention]

The method for manufacturing bipolar transistors using triple diffusion is as follows:
This method has the advantage that the manufacturing process is simple because it does not require the step of growing an epitaxial layer and the step of separating this epitaxial layer with an isolation oxide film.

A method of manufacturing a bipolar transistor using the above-mentioned triple diffusion will be explained with reference to FIG.

First, a thermal oxide film 2 is formed on the surface of a P- type silicon substrate 1, and then, for example, p+-e ions are implanted into a predetermined region of the substrate 1, and a heat treatment is performed to form an N- type collector region 3. Next, a highly doped N+ type collector contact region 47 is formed in this N- type collector region 3 in order to lower the collector series resistance. Next, the N-type collector region 3
Bi ions are implanted into a predetermined region within the P
- Form the entire mold pace area 5.

Next, A is applied to a predetermined area within this P-type pace area 5.
N+ type emitter region 6 is formed by sf ion implantation and heat treatment. Next, holes are formed in the thermal oxide film 2, and emitter, paste, and collector electrodes are formed, and the NP
Manufacture N bipolar transistor.

[Problems with background technology]

The ion implantation used in the above method is so-called random ion implantation, and the impurity concentration distribution in each region of the manufactured bipolar transistor is as shown in FIG. As is clear from FIG. 2, the impurity concentration in the collector region C decreases as the depth from the substrate surface increases. Therefore, there is a drawback that the series resistance of the collector increases and the switching operation of the transistor is significantly inhibited.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks, and provides a method for manufacturing a bipolar semiconductor device that can achieve high speed.
It seeks to provide the law.

[Summary of the invention]

When impurity ions are randomly implanted as in the conventional method, the impurities are as shown by the broken lines in Fig. 3 (L, S,
S, according to theory, takes a Gaussian distribution with maximum concentration at range (Rp). On the other hand, the impurity ions are aligned with the crystal axes of the semiconductor substrate, for example (110), <112>, (100), <
When ions are implanted substantially parallel to the 111> direction, impurities abnormally invade the crystal as shown by the broken line in FIG. A so-called channeling phenomenon occurs, and a distribution with a maximum concentration is taken at Rch inside the crystal (hereinafter referred to as the above-mentioned ion implantation and full channeling ion implantation).

The present invention applies the above channeling ion implantation to the formation of a collector of a bipolar transistor by active triple diffusion. That is, in the method of manufacturing a bipolar semiconductor device of the present invention, impurity ions of the second conductivity type are selectively implanted into a semiconductor substrate of the first conductivity type substantially parallel to the crystal axis direction of the substrate to form a semiconductor substrate of the second conductivity type. a step of forming the entire collector region, a step of forming the entire base region of the first conductivity type within the collector region of the second conductivity type, and a step of forming an emitter region of the second conductivity type within the space region of the first conductivity type. The method is characterized by comprising a step of:

When channeling ion implantation is applied to form the collector region in this way, the impurity concentration distribution is different from that in Figure 2.
It will look like the figure. Therefore, the concentration inside the collector region can be made about one order of magnitude higher than the concentration near the entire surface.
Higher speeds can be achieved by reducing the series resistance of the collector.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to FIGS.

First, P with a plane orientation (110) and a specific resistance of 10 to 20 Ω・m
- Oxide film 1 with a thickness of 0.3 μm on the surface of the silicon substrate 11
2'ff: Formed. Next, after selectively etching and removing a part of this oxide film 12 to form an opening 13,
Diffuse at 1000°C for 30 minutes as a ct3'i diffusion source,
ρ8=3, x j" 1-5 Aim ON+ type collector extraction region 14 was formed (as shown in Fig. 5(,))
.

Next, after the oxide film 12 was completely removed by etching, photoresist holes and turns 15 were etched in areas other than the portion where the collector region was to be formed.

Continuing, the incident direction of P ions and the corner 1 of the substrate 11
10> After aligning the crystal axes within ±o, 3 e・, apply p'6 acceleration energy 1 to the area where the collector region is to be formed.
Channeling ions were implanted under the conditions of 50 keV and a dose of 4×10 15 crn-2 (as shown in FIG. 5(b)).

Next, after removing the photoresist pattern 15,
A thermal oxide film 16 with a thickness of 0.1 μm was formed on the entire surface. At this time, the P ion implantation layer is simultaneously activated, and xj=1
．． 5 μm 1 surface concentration 1 o crn 1 crystal inside 10
An N-type collector region 17 was formed with a peak concentration of cm 2 . Subsequently, the thermal oxide film 16 is coated with a thickness of 0.
A 1 μm silicon nitride film 18 was deposited (Fig. 5(C)).
(Illustrated).

Next, a thickness of 1.0 μm was applied to cover the area other than the area where the pace area is to be formed.
After applying a photoresist pattern 19 of m, B + total acceleration energy of 100 keV.

Ion implantation was performed at a dose of lXl0 cm (as shown in FIG. 5(d)).

Next, after removing the photoresist pattern 19,
After heat treatment at 1000℃ for 1.5 minutes in N2 atmosphere, ρ,
A P-type base region 20 of =500Ω/hole and x j ”” of 0.4 μm was formed. Subsequently, portions of the silicon nitride film 18 and the thermal oxide film 16 corresponding to the portion where the emitter region is to be formed and the portion where the collector contact region is to be formed are sequentially and selectively removed to form openings 21°21. Thereafter, ions were implanted under the conditions of As k acceleration energy of 60 keV and dose of 2 x 1015 cm-2 (as shown in Fig. 5(, )).

Next, heat treatment was performed at 1000° C. for 15 minutes in an N2 atmosphere to form a type 1 emitter region 22 and an N+ type collector contact region 23 with Xj of 70.2 μm. Subsequently, a portion of the silicon nitride film 18 and the thermal oxide film 16 corresponding to the P-type base region 20 were selectively etched away in order to form an opening 24. It comes with AA- on the entire surface.
After depositing the 8t film, it is patterned to form the emitter electrode 2.
5. Form the base electrode 26 and collector electrode 27, and
2H Nogipola Tranlista tray was manufactured (Fig. 5 (
f) As shown).

Thus, according to the method of the present invention, an N-type collector region 17 having an optical surface concentration of 1017 m-3 and a peak concentration of 1018 cm-' inside the crystal can be formed by channeling P ion implantation. Therefore, since the collector series resistance can be reduced, higher speeds can be achieved. In addition, the use of channeling ion implantation preserves the crystallinity of the collector region.
A good base-collector junction can be formed.

Note that in the above example, channeling ion implantation of impurity ions was performed approximately parallel to the <11'0> crystal axis of the semiconductor substrate with the (110) plane orientation; ) A similar effect can be obtained by performing channeling ion implantation approximately parallel to the axis.

Also, the plane orientation (100), (111) or (112
It goes without saying that the channeling ion implantation may be carried out substantially parallel to the (100) axis, (111) axis, or <112> axis of the semiconductor substrate.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a complete method of manufacturing a bipolar semiconductor device that can achieve high speed.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a bipolar transistor manufactured by conventional triple diffusion, Figure 2 is a diagram showing the impurity concentration distribution of the same bipolar transistor, and Figure 3 is the impurity concentration of random ion implantation and channeling ion implantation. FIG. 4 is a diagram showing the entire distribution, and FIG. 4 is a diagram showing the impurity concentration distribution of a bipolar transistor manufactured by the method of the present invention. FIG.
(f) is a sectional view showing the entire manufacturing process of a bipolar transistor according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 11...P-type silicon substrate, 14...1 type collector extraction region, 16...thermal oxide film, 17...N type collector region, 18...silicon nitride film, 20...P
Type base region, 22...1 type emitter region, 25...
- Emitter electrode, 26...base electrode, 27...collector electrode. Applicant's agent Patent attorney Takehiko Suzue 1st Sou.
d 3rd IJ table iO・Rari; inclusion 2nd H stone 4 11! (1 Tadasu Command・Ranokiki (a) (c) - (d)

Claims (1)

[Claims] forming a collector region of the second conductivity type by selectively ion-implanting a second conductivity type impurity into the semiconductor substrate of the first conductivity type substantially parallel to the crystal axis direction of the substrate; A bipolar semiconductor device comprising the steps of: forming a first conductivity type paste region within the collector region; and forming a second conductivity type emitter region within the first conductivity type paste region. manufacturing method.