JPS5986757U - Muting circuit - Google Patents
Muting circuitInfo
- Publication number
- JPS5986757U JPS5986757U JP18319682U JP18319682U JPS5986757U JP S5986757 U JPS5986757 U JP S5986757U JP 18319682 U JP18319682 U JP 18319682U JP 18319682 U JP18319682 U JP 18319682U JP S5986757 U JPS5986757 U JP S5986757U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- muting
- circuit
- chopper
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Noise Elimination (AREA)
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係るスイッチング方式のＦＭステレオ
受信機の実施例を示す図である。第２図は本考案のミュ
ーティング回路の主要部の実施例を示す回路図である。
１：アンテナ、２：フロントエンド、３：中間周波増幅
回路、４．ＦＭ検波回路、５：復調信号発生回路、６：
駆動回路、８：チョッパ回路、９：整流平滑回路１３を
具えたミューティングレベル検出回路、１０：加算回路
、１１．１２：出力端子。FIG. 1 is a diagram showing an embodiment of a switching type FM stereo receiver according to the present invention. FIG. 2 is a circuit diagram showing an embodiment of the main parts of the muting circuit of the present invention. 1: Antenna, 2: Front end, 3: Intermediate frequency amplification circuit, 4. FM detection circuit, 5: demodulation signal generation circuit, 6:
Drive circuit, 8: Chopper circuit, 9: Muting level detection circuit including rectification and smoothing circuit 13, 10: Addition circuit, 11.12: Output terminal.
Claims (1)
てその他端を共通接続した差動増幅器からなる加算回路
と、該加算回路の入力端間に一対のトランジスタからな
るチョッパ回路を具え、該チョッパ回路の夫々のトラン
ジスタのベースに互い１−こ位相の反転した３８ＫＨ２
副搬送波信号を入力して複合信号を分離するスイッチン
グ方式のＦＭステレオ受信機に於て、受信信号レベルが
ミュー′、 ティングレベルに達したとき、該チョ
ッパ回路をなす二つのトランジスタを同時に動作状態と
することによって信号伝送系にミューティングを掛ける
ことを特徴とするＦＭステレオ受信機のミューティング
回路。An adder circuit consisting of a differential amplifier in which an emitter resistor is connected to the emitters of a pair of transistors and the other ends are connected in common, and a chopper circuit consisting of a pair of transistors is provided between the input terminals of the adder circuit, and each of the chopper circuits 38KH2 with opposite phases to each other at the bases of the transistors.
In a switching type FM stereo receiver that inputs a subcarrier signal and separates a composite signal, when the received signal level reaches the muting level, the two transistors forming the chopper circuit are simultaneously activated. A muting circuit for an FM stereo receiver, characterized in that muting is applied to a signal transmission system by doing so.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18319682U JPS5986757U (en) | 1982-12-03 | 1982-12-03 | Muting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18319682U JPS5986757U (en) | 1982-12-03 | 1982-12-03 | Muting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5986757U true JPS5986757U (en) | 1984-06-12 |
| JPS6238364Y2 JPS6238364Y2 (en) | 1987-09-30 |
Family
ID=30396542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18319682U Granted JPS5986757U (en) | 1982-12-03 | 1982-12-03 | Muting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5986757U (en) |
-
1982
- 1982-12-03 JP JP18319682U patent/JPS5986757U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6238364Y2 (en) | 1987-09-30 |
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