JPS5936647U - Stereo/monaural switching circuit - Google Patents
Stereo/monaural switching circuitInfo
- Publication number
- JPS5936647U JPS5936647U JP13216382U JP13216382U JPS5936647U JP S5936647 U JPS5936647 U JP S5936647U JP 13216382 U JP13216382 U JP 13216382U JP 13216382 U JP13216382 U JP 13216382U JP S5936647 U JPS5936647 U JP S5936647U
- Authority
- JP
- Japan
- Prior art keywords
- stereo
- circuit
- transistors
- multiplier
- bases
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案のステレオ・モノラル切換回路を具えた
ステレオ復調回路の一実施例である。
１ニーフロントエンド、２：中間周波増幅段、３：リミ
ッタ回路、４：ＦＭ検波回路、５：掛算器、６：チョッ
パ回路、７：ステレオ復調回路、８ ：３８ＫＨｚスイ
ッチンク信号発生回路、９：Ｌ／ベルシフト回路、１０
：１９ＫＨｚパイロット信号の有無を検出する回路、１
１：制御回路、１２． １３：負荷回路、１４．１５：
出力端子、１６：電流源回路。FIG. 1 shows an embodiment of a stereo demodulation circuit equipped with a stereo/monaural switching circuit according to the present invention. 1 knee front end, 2: intermediate frequency amplification stage, 3: limiter circuit, 4: FM detection circuit, 5: multiplier, 6: chopper circuit, 7: stereo demodulation circuit, 8: 38KHz switching signal generation circuit, 9: L/bell shift circuit, 10
:Circuit for detecting the presence or absence of a 19KHz pilot signal, 1
1: Control circuit, 12. 13: Load circuit, 14.15:
Output terminal, 16: Current source circuit.
Claims (1)
第４のＮＰＮ トランジスタのベース間に夫々抵抗が接
続され、該第１乃至第４のトランジスタのエミッタに抵
抗が接続され該抵抗の夫々の他端が共通接続された差動
対からなり、ステレオ複合信号が供給される該掛算器の
入力端間に第１と第２のＰＮＰトランジスタからなるチ
ョッパ回路を具えてステレオ復調回路を形成し、ステレ
オ受信時は該第１と第２のＰＮＰ トランジスタのベー
スにステレオ復調信号がレベルシフト回路を介し入力さ
れ、該レベルシフト回路によって電流源回路に互いのエ
ミッタを共通接続した第３と第４のＰＮＰ ）ランジス
タのベースにステレオ復調信号が供給されてレベルシフ
トされたステレオ復調信号が該チョッパ回路に供給され
該掛算器に入力されたステレオ複合信号の左信号と右信
号が分離されるようになされ、且つモノラル受信時は該
レベルシフト回路の該電流源回路を遮断してステレオ復
調信号のチョッパ回路への供給を断つと共に、該掛算器
をなす２つのトランジスタ対の一つを遮断することを特
徴とするステレオ・モノラル切換回路。A multiplier is connected between the bases of the first and second transistors and between the bases of the third and fourth NPN transistors, and a resistor is connected to the emitters of the first to fourth transistors. A stereo demodulation circuit is formed by providing a chopper circuit consisting of a first and a second PNP transistor between the input terminals of the multiplier, which is composed of a differential pair whose other ends are commonly connected, and is supplied with a stereo composite signal. However, during stereo reception, a stereo demodulated signal is input to the bases of the first and second PNP transistors via a level shift circuit, and the third and second PNP transistors, whose emitters are commonly connected to the current source circuit, are input by the level shift circuit to the bases of the first and second PNP transistors. PNP 4) A stereo demodulated signal is supplied to the base of the transistor, and the level-shifted stereo demodulated signal is supplied to the chopper circuit so that the left signal and right signal of the stereo composite signal input to the multiplier are separated. and at the time of monaural reception, cut off the current source circuit of the level shift circuit to cut off the supply of the stereo demodulated signal to the chopper circuit, and cut off one of the two transistor pairs forming the multiplier. A stereo/monaural switching circuit featuring the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13216382U JPS5936647U (en) | 1982-08-31 | 1982-08-31 | Stereo/monaural switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13216382U JPS5936647U (en) | 1982-08-31 | 1982-08-31 | Stereo/monaural switching circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5936647U true JPS5936647U (en) | 1984-03-07 |
Family
ID=30298553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13216382U Pending JPS5936647U (en) | 1982-08-31 | 1982-08-31 | Stereo/monaural switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5936647U (en) |
-
1982
- 1982-08-31 JP JP13216382U patent/JPS5936647U/en active Pending
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