JPS6322748Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a muting circuit for a switching type FM stereo receiver.

The muting circuit of the present invention is a muting circuit suitable for semiconductor integrated circuits, and is formed by adding very few circuit elements to an existing switching type FM stereo receiver. Conventional muting circuits have the disadvantage of increasing the number of components because field effect transistors and large capacitance capacitors are added to the circuit in which the audio circuit is integrated.

The main purpose of this invention is to
The purpose of the present invention is to provide a muting circuit suitable for a stereo receiver.

Another object is to reduce the number of components in the muting circuit and provide an inexpensive muting circuit for an FM stereo receiver.

Still another object is to provide a muting circuit that suppresses the generation of pop noise during a muting operation.

Another object of the present invention is to provide a muting circuit suitable for semiconductor integrated circuit implementation.

The muting circuit of the present invention has been made to achieve the above-mentioned purpose, and includes a chopper circuit that time-divides a composite signal using a demodulated signal;
This muting circuit is suitable for a switching type FM stereo receiver that includes a decoder circuit consisting of an adder circuit that adds the signals. That is,
When the received signal reaches a muting operation level, a muting signal is generated to activate a switch circuit connected in parallel to the chopper circuit,
This is a muting circuit that applies muting to the signal transmission system by keeping the impedance between the terminals of the chopper circuit low.

Hereinafter, the muting circuit of the present invention will be explained based on FIGS. 1 to 4.

In Figure 1, 1 is an antenna, 2 is a front end, 3 is an intermediate frequency amplification circuit, 4 is an FM detection circuit, 5 is a 38KHz subcarrier signal generation circuit, 6 is a drive circuit, and 7 is a mutating level detection circuit. circuit, 8
9 is a chopper circuit, 9 is a switch circuit, and 10 is an adder circuit.

Switching type FM stereo receiver is FM
A 19KHz pilot signal is obtained from the composite signal obtained by the detection circuit 4 by the demodulation signal generation circuit 5,
Furthermore, the signal is multiplied to obtain a 38KHz demodulated signal,
The composite signal supplied to the bases of the transistors Q ₁ and Q ₂ of the chopper circuit 8 through the drive circuit 6 and supplied from the FM detection circuit 4 is time-divided by the chopper circuit and supplied to the adder circuit 10. This is a method that

Now, the configuration of the main parts of the muting circuit of the present invention will be explained. The adder circuit 10 consists of transistors Q ₅ and Q ₆ , whose collectors and power supply terminal 1
A load resistor R _L is connected between each of the terminals 3 and 3, and emitter resistors R ₅ and R ₆ are connected to their emitters, and the other ends of the emitter resistors R ₅ and R ₆ are commonly connected and grounded through a resistor R ₇ . . A resistor _R4 is connected to the base of the transistor _Q5 , a resistor _R3 is connected to the base of the transistor _Q6 , and a resistor is connected to the other ends of the resistors _R3 and _R4 .
R ₁ and R ₂ are connected, and the other ends are commonly connected to a coupling capacitor C. The chopper circuit 8 is formed from PNP transistors Q ₁ and Q ₂ , and the collector of PNP transistor Q ₁ is connected to a resistor.
Connected to the connection point of R ₁ and R ₃ , a PNP transistor
The collector of Q ₂ is connected to the connection point of resistors R ₂ and R ₄ ,
The emitters of PNP transistors Q ₁ and Q ₂ are commonly connected and connected to a DC voltage source 14 . and,
Resistors are installed at the bases of PNP transistors Q ₁ and Q ₂ , respectively.
R ₈ and R ₉ are connected. The switch circuit 9 to which the muting signal is supplied consists of PNP transistors Q ₃ and Q ₄ , similar to the chopper circuit 8.
The collector of transistor Q ₃ is connected to the connection point of resistors R ₁ and R ₃ , the collector of PNP transistor Q ₄ is connected to the connection point of resistors R ₂ and R ₄ , and the emitters of PNP transistors Q ₃ and Q ₄ are common. and is connected to a DC voltage source 14. The collector of a transistor _Q7 is connected to the bases of the PNP transistors _Q3 and _Q4 , the base thereof is connected to the muting level detection circuit 7, and the emitter is grounded.

When the input level of the input signal is sufficiently large, the 38KHz demodulated signals with mutually inverted phases are input to the chopper circuit 8, and the composite signal is time-divided and input to the adder circuit 10, where the composite signal is stereo-separated. At this time, the transistor of switch circuit 9
Q ₃ and Q ₄ are in the off state. Furthermore, during monaural reception, the chopper circuit 8 stops operating and the in-phase composite signal is input to the adder circuit 10.

Now, the muting motion will be explained.
The input signal level is detected by a muting level detection circuit 7. The output from the intermediate frequency amplifier circuit 3 is rectified and smoothed by the muting level detection circuit 7, and when it is detected that a predetermined muting operation level has been reached, the transistor
Activate _Q7 to turn on switch circuit 9. This prevents the composite signal from being input to the adder circuit 10 and applies muting. During the muting operation, the switch circuit 9 has a low impedance and the composite signal is grounded in an alternating current manner, so that the composite signal is not applied to the adder circuit 10.
Therefore, muting is applied to the signal transmission system.
Since DC voltage is applied from the DC voltage source 14 to the bases of the transistors Q ₅ and Q ₆ of the adder circuit 10 and the DC level of the output terminals 11 and 12 is substantially constant even during the muting operation, pop noise can be suppressed. can. Furthermore, since the muting circuit of the embodiment shown in FIG. 1 can be formed by simply adding three transistors, it is easy to integrate into a semiconductor integrated circuit, and the number of parts is small, making it effective for inexpensive FM stereo receivers.

In the embodiment shown in FIG. 2, resistors R ₈ and R 9 are connected to the collector sides of transistors Q ₃ and Q ₄ forming the switch circuit _9.
is connected. This allows the composite signal input from the coupling capacitor C to be attenuated to a desired level. Furthermore, the same effect can be obtained by adding a resistor to the emitter side of the transistors Q ₃ and Q ₄ . The rest is the same as the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing one embodiment of the drive circuit 6. A 38 KHz demodulated signal is input from the demodulated signal generation circuit 5 to the chopper circuit 8 via the drive circuit 6. In the drive circuit 6, the emitters of transistors Q ₈ and Q ₉ are commonly connected to a current source 13, and resistors R ₁₂ and R ₁₃ are connected to their collectors.
The base of the transistor _Q10 is connected to the connection point between the collector of the transistor _Q8 and the resistor _R12 , and the resistor _R14 is connected to the collector of the transistor _Q10 .
The base of the transistor Q ₁₁ is connected to the connection point between the collector of the transistor Q ₉ and the resistor R ₁₃ , the resistor R ₁₅ is connected to the collector of the transistor Q ₁₁ , and the DC voltage source 15 is connected to the other ends of the resistors R ₁₄ and R ₁₅ . is connected. A resistor _R9 is connected to the connection point a between the resistor _R14 and the collector of the transistor _Q10 , and the other end is connected to the base of the transistor _Q2 of the chopper circuit 8. Further, a resistor _R8 is connected to the connection point b between the collector of the transistor _Q11 and the resistor _R15 ,
A resistor _R8 is connected to the other end, which is connected to the base of the transistor _Q1 .

During stereo reception, the 38KHz demodulated signal is sent to drive circuit 6.
is input. Transistors Q ₈ and Q ₉ are alternately turned on and off by a 38KHz demodulated signal. When transistor _Q8 is on (off),
The transistor Q ₁₀ is turned on (off), and the transistor Q ₂ of the chopper circuit 8 is also turned on (off). Similarly, when transistor Q ₉ is off (on), transistor Q ₁₁ is off (on),
Transistor _Q1 of chopper circuit 8 is off (on)
becomes. In this way, the 38 KHz demodulated signal is inputted via the drive circuit 6, and the transistors Q ₁ and Q ₂ are operated alternately to perform time division and stereo separation of the composite signal. Also, when receiving monaural signals, the transistor
A stereo signal is connected to the commonly connected emitters of Q ₈ and Q ₉ .
A monaural switching signal A is supplied to set the monaural reception state. Even in this state, it is of course possible to apply mutating.

The muting circuit in Figure 4 is a chopper circuit 8.
and the transistors that make up the switch circuit 9 are
It is formed of an NPN transistor, and the muting signal is supplied to the base of transistor _Q16 . Transistor forming switch circuit 9
The emitter of transistor Q ₁₆ is connected to the base of Q 15 _{and Q 16 ,} and the resistor is connected to the collector of transistor Q ₁₆ .
_R10 is connected, and the other end is connected to terminal 13. A DC voltage source 14 is connected to a common connection point between the collectors of transistors Q ₁₅ and Q ₁₆ .

In the embodiment shown above, in the FM stereo receiver using the muting circuit of the present invention, the load circuit of the adder circuit 10 is formed by the resistor R _L , but it can be formed by an active load circuit such as a current mirror circuit.

As mentioned above, the muting circuit of the present invention is suitable for a switching type FM stereo receiver. That is, a muting circuit can be formed by adding a similar transistor circuit in parallel to the chopper circuit. Needless to say, such a system cannot form a muting circuit in a matrix type FM stereo receiver. Furthermore, since the switch circuit is formed of two transistors, it is easy to integrate the switch circuit into a semiconductor integrated circuit, which has the advantage of providing an inexpensive FM stereo receiver. Furthermore, since the base potential of the transistor forming the adding circuit does not vary when the muting circuit is in operation, it is possible to suppress the occurrence of pop noise. Furthermore, the volume attenuation level during muting can be adjusted by adding a resistor to the collector or emitter side of the transistor forming the switch circuit.

As mentioned above, the muting circuit of the present invention has various effects and is extremely effective.

[Brief explanation of the drawing]

FIG. 1 shows a switching type FM stereo receiver equipped with a muting circuit according to the present invention. FIG. 2 is a diagram showing an application example of the muting circuit of the present invention. FIG. 3 is a diagram showing an embodiment of the peripheral circuit of the muting circuit. FIG. 4 is a diagram of a switching type FM stereo receiver showing another embodiment of the muting circuit according to the present invention. 1: Antenna, 2: Front end, 3: Intermediate frequency amplification circuit, 4: FM detection circuit, 5: Demodulation signal generation circuit, 6: Drive circuit, 7: Muting level detection circuit, 8: Chopper circuit, 9: Switch Circuit, 10: Addition circuit.

Claims (1)

[Scope of utility model registration request] In a switching type FM switch receiver, the FM detection output is has first and second signal input stages that distribute the signal into two systems and supply the signal to the base of the transistor of the decoder circuit, and an emitter is commonly connected between the first and second signal input stages. The collectors of the first and second transistors are respectively connected to a bias voltage source, and a demodulating subcarrier signal is supplied to the bases of the first and second transistors, respectively. The collectors of third and fourth transistors whose emitters are connected in common and connected to the bias voltage source are respectively connected between the second signal input stage, and the bases of the third and fourth transistors are connected to each other. A mutating circuit characterized in that a muting signal is supplied.