JPS5986756U - Muting circuit - Google Patents
Muting circuitInfo
- Publication number
- JPS5986756U JPS5986756U JP18319582U JP18319582U JPS5986756U JP S5986756 U JPS5986756 U JP S5986756U JP 18319582 U JP18319582 U JP 18319582U JP 18319582 U JP18319582 U JP 18319582U JP S5986756 U JPS5986756 U JP S5986756U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- muting
- resistors
- transistors
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Noise Elimination (AREA)
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係るミューティング回路を具えたスイ
ッチング方式のＦＭステレ芽受信機である。２第２図は
本考案のミューティング回路の応用例を示す図である。
第３図はミューティング回路 □の周辺回路の実施例
を示す図である。第４図は本考案に係るミューティング
回路の他の実施例を示すスイッチング方式のＦＭステレ
オ受信機の図である。
１：アンテナ、２：フロントエンド、３：中間周波増幅
回路、４．ＦＭ検波回路、５：復調信号発生回路、６：
駆動回路、７：ミューティングレベル検出回路、８：チ
ョッパ回路、９：スイッチ回路、１０：加算回路。FIG. 1 shows a switching type FM stereo receiver equipped with a muting circuit according to the present invention. 2 FIG. 2 is a diagram showing an application example of the muting circuit of the present invention. FIG. 3 is a diagram showing an embodiment of the peripheral circuit of the muting circuit □. FIG. 4 is a diagram of a switching type FM stereo receiver showing another embodiment of the muting circuit according to the present invention. 1: Antenna, 2: Front end, 3: Intermediate frequency amplification circuit, 4. FM detection circuit, 5: demodulation signal generation circuit, 6:
Drive circuit, 7: Muting level detection circuit, 8: Chopper circuit, 9: Switch circuit, 10: Adder circuit.
Claims (5)
にエミッタ堺抗を接続し、該エミッタ抵抗の他端を共通
接続した差動増幅器からなる加算回路と、該加算回路の
入力段に互いに位相の反転した復調用副搬送波信号によ
って制御されたチョッパ回路を具えたスイッチング方式
のＦＭステレオ受信機に於て、ミューティング信号によ
って制御されるスイッチ回路が該チョッパ回路に並列に
接続され、該スイッチ回路をミューティング動作時に低
インピーダンスとして信号′ 伝送系にミューテ
ィングを掛けることを特徴とするミューティング回路。(1) An adder circuit consisting of a pair of transistors, a differential amplifier in which an emitter resistor is connected to the emitter of the transistor, and the other end of the emitter resistor is connected in common; In a switching type FM stereo receiver equipped with a chopper circuit controlled by a demodulating subcarrier signal, a switch circuit controlled by a muting signal is connected in parallel to the chopper circuit, and the switch circuit is muted. A muting circuit characterized by applying muting to a signal transmission system with low impedance during operation.
レクタに夫々負荷回路が接続され、該第１と第２
のトランジスタのエミッタに夫々エミッタ抵抗が接続さ
れ、該エミッタ抵抗の他端が共通接続されてなる差動増
幅器からなり、該第１と該第２のトランジスタのベース
に第１と第２の抵抗が接続され、該第１と該第２の抵抗
の他端に第３と第４の抵抗が接続され、該第３と該第４
の抵抗の他端が共通接続され、該第１と該第３の抵抗の
接続点と該第２と該第４の抵抗の接続点にミューティン
グ信号によって制御されたスイッチ回路とチョッパ回路
が並列に接続された実用新案登録請求の範囲第１項記載
のミューティング回路。(2) The adder circuit connects the first and second transistors.
A load circuit is connected to each of the first and second
The differential amplifier comprises a differential amplifier in which an emitter resistor is connected to the emitter of each of the transistors, and the other ends of the emitter resistors are connected in common, and a first resistor and a second resistor are connected to the bases of the first and second transistors. and third and fourth resistors are connected to the other ends of the first and second resistors, and the third and fourth resistors are connected to the other ends of the first and second resistors.
The other ends of the resistors are commonly connected, and a switch circuit and a chopper circuit controlled by a muting signal are connected in parallel to the connection point between the first and third resistors and the connection point between the second and fourth resistors. The muting circuit according to claim 1 of the utility model registration, which is connected to the muting circuit.
スタからなり、該第１と該第２のＰＮＰ トランジスタ
の共通接続されたエミッタに直流電圧源が接続され、ミ
ューティング動作時に該加算回路をなす該第１と該第２
のトランジスタのベースに該直流電圧源からバイアス電
圧を供給してポツプノイズの発生を抑圧した実用新案登
録請求の範囲第２項記載のミューティング回路。(3) The switch circuit includes first and second PNP transistors, a DC voltage source is connected to the commonly connected emitters of the first and second PNP transistors, and the adder circuit is connected during muting operation. The first one and the second one
3. The muting circuit according to claim 2, wherein the occurrence of pop noise is suppressed by supplying a bias voltage from the DC voltage source to the base of the transistor.
Ｐ ）ランジスタのエミッタ或いはコレクタに夫々抵抗
を接続してミューティング動作時の減衰レベルを設定す
る実用新案登録請求の範囲第２ 項記載のミューティン
グ回路。(4) The first and second PNs included in the switch circuit
P) The muting circuit according to claim 2, which sets the attenuation level during muting operation by connecting resistors to the emitters or collectors of the transistors.
スタからなり、該第１と該第２のＮＰＮ ）う、 ン
ジスタのエミッタを共通接続して直流電圧源が接続され
た実用新案登録請求の範囲第２項記゛載のミューティン
グ回路。(5) A utility model registration claim in which the switch circuit is composed of first and second NPN transistors, and the emitters of the first and second NPN transistors are connected in common and a DC voltage source is connected. The muting circuit described in Range 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18319582U JPS5986756U (en) | 1982-12-03 | 1982-12-03 | Muting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18319582U JPS5986756U (en) | 1982-12-03 | 1982-12-03 | Muting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5986756U true JPS5986756U (en) | 1984-06-12 |
| JPS6322748Y2 JPS6322748Y2 (en) | 1988-06-22 |
Family
ID=30396540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18319582U Granted JPS5986756U (en) | 1982-12-03 | 1982-12-03 | Muting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5986756U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5348507U (en) * | 1976-09-28 | 1978-04-24 | ||
| JPS5753771U (en) * | 1980-09-12 | 1982-03-29 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54103814A (en) * | 1978-02-02 | 1979-08-15 | Showa Denko Kk | Continuous preparation of ethylene glycol monoethyl ether acetate |
-
1982
- 1982-12-03 JP JP18319582U patent/JPS5986756U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5348507U (en) * | 1976-09-28 | 1978-04-24 | ||
| JPS5753771U (en) * | 1980-09-12 | 1982-03-29 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6322748Y2 (en) | 1988-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US2762874A (en) | Semi-conductor signal amplifier circuits | |
| JP3382128B2 (en) | Differential amplifier | |
| US4864248A (en) | Amplifier arrangement with controllable gain | |
| JPS5986756U (en) | Muting circuit | |
| JPS645370Y2 (en) | ||
| JPS6125264B2 (en) | ||
| US4236253A (en) | Monostable multivibrator for use in pulse count demodulator or the like | |
| US4056783A (en) | Linear sound amplifier circuit | |
| JPS5986757U (en) | Muting circuit | |
| JPH0533080Y2 (en) | ||
| JPS5831780B2 (en) | FM Jiyushinki | |
| JPS6029222Y2 (en) | amplifier | |
| JPH0332110Y2 (en) | ||
| JPS5936647U (en) | Stereo/monaural switching circuit | |
| JPS604261Y2 (en) | tape recorder | |
| JPH0528825Y2 (en) | ||
| JPS58189634U (en) | FM receiver muting circuit | |
| JPS6241447Y2 (en) | ||
| JPH0125040Y2 (en) | ||
| JPS59100607A (en) | Differential amplifier | |
| JPH0345567B2 (en) | ||
| JPS6133706Y2 (en) | ||
| JPH0156581B2 (en) | ||
| JPH03117907A (en) | Amplifier with muting circuit | |
| JPS63140780U (en) |