JPS645370Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a signal output circuit, and particularly to an output circuit having a constant output impedance over a wide band.

[Background technology and its problems]

Since the IF signal output from a TV tuner has frequency components in a wide band, it is generally transmitted to a predetermined location using a cable or the like with low impedance characteristics.

FIG. 1 shows the output stage of such an IF signal, where Q is a transistor for impedance conversion,
R _e is a bias resistor, R _n is a resistor that matches the output impedance of the transistor Q with the impedance R _L of the coaxial cable that serves as the load,
C is a capacitor that cuts DC.

The output impedance Zout of the transistor Q is the bias resistance R _e and the input side impedance Zin
e.g. input impedance
If Zin is small, the output impedance Zout
(30Ω) from the cable characteristic impedance R _L
(75Ω), the matching resistor R _n cannot be omitted.

Then the signal voltage supplied to the cable load
E′ ₀ is compared with the output voltage E ₀ of transistor _Q , and becomes E′ ₀ =R _L /R _n +R _L −E ₀ , and transistor Q is equal to (1+R _n /R _L ) It is necessary to output a signal with twice the amplitude.

However, there is a problem in that increasing the amplitude of the output signal by increasing the operating voltage source of the transistor Q is not preferable from the viewpoint of power saving.

[Purpose of invention]

This idea was devised in view of the actual situation. Even when a matching resistor is used, the signal component is supplied to the load without any attenuation, and the desired amplitude can be achieved even at a low power supply voltage. This provides a constant impedance circuit that provides certain characteristics.

[Summary of the idea]

In order to achieve the above object, this invention connects a second transistor in cascade to the first transistor forming an output stage, and connects the load with the matching resistor connected to the second transistor. The value of each resistor is set so that impedance matching of the output stage is performed and at the same time a predetermined output signal is obtained.

〔Example〕

Figure 2 shows an embodiment of the constant impedance circuit of this invention, where Q ₁ is a transistor for signal inversion, Q ₂ and Q ₃ are a pair of transistors forming the output stage, and R _n is a matching transistor. The resistance, R _e , is the bias resistance.

In addition, C is a capacitor for DC cut, R _L
indicates load resistance.

The operation of this circuit will be explained below.

If the emitter current of transistor Q ₃ is i _e3 , the collector current of transistor Q ₂ is i _c2 , and the current flowing through the load resistor R _L is i ₀ , then i _e3 = i _c2 + i ₀ ...(1) Here, transistor Q If the current amplification factor of ₂ is large enough, then i _c2 i _e2 , and the transistor
Assuming that Q ₂ operates as an emitter follower with a gain of 1, i _e2 = e _i /R _e (2) (where e _i is the input signal).

Therefore, the equation (1) becomes: i _e3 =e _i /R _e +e ₀ /R _L (3) (where e ₀ is the output signal).

By the way, the collector signal of transistor _Q1 is
If e ₁ , then e ₁ = R _n・i _e3 + e ₀ ...(4), and if the voltage gain of transistor Q ₁ is G, then e ₁ = −e _i・G ...(5) Therefore, From equation (4), e ₀ = −R _n・i _e3 −e _i・G ...(6) Therefore, by substituting equation (6) into equation (3), i _e3 = e _i /R _e − (R _n・i _e3 +e _i・G/R _L ) ...(7) (1+R _n /R _L )i _e3 = (1/R _e −G/R _L )e _i ...(8) If R _e =R _L /G, that is, the ratio of the load resistance value R _L to the bias resistance value R _e is made proportional to G indicating the ratio of e ₁ to e _i , i _e3 =0.

Therefore, if the circuit constants are determined as described above, only a DC voltage drop will occur across the matching resistor R _n , and all signal components will be supplied to the load resistor R _L.

In other words, by inserting a resistor R _n , impedance matching between the output stage and the load resistor R _L is achieved.
In addition, a circuit that does not cause loss to the output signal component can be constructed, resulting in a particularly excellent output stage as a constant impedance circuit.

Above we have explained (NPN) type transistors Q ₁ , Q ₂ , Q ₃ , but as shown in Figure 3, (PNP)
It goes without saying that transistors Q' ₁ , Q' ₂ , Q' ₃ of the same type may also be used.

Furthermore, since the transistor _Q1 is used as a phase inverter in FIG. 2, the input of the transistor _Q3 may be connected to the emitter of the transistor _Q1 as shown by the dotted line.

Furthermore, as shown in _FIG.
consists of a differential amplifier A, and a transistor Q ₂
It can also be designed such that the non-inverted input signal e _i is applied to the input of the transistor Q ₃ and the inverted input signal -G·e _i is applied to the input of the transistor Q 3 .

In this case, if the input signal of transistor Q ₂ is ne _i , the above equation (3) becomes i _e3 = ne _i /R _e +e ₀ /R _L (3'), and the equation (8 ) is (1+R _n /R _L )i _e3 = (n/R _e −G ₁ /R _L )e _i ...(8
') (G ₁ is the gain of the inverted signal by differential amplifier A) However, if R _e =nR _L /G ₁ is chosen, i _e3 =0, and the same effect is achieved.

[Effect of idea]

As explained above, in the constant impedance circuit of this invention, even when a resistor (R _n ) for impedance matching is inserted in the output stage, the signal component does not suffer loss due to this resistor (R _n ). This has the advantage that the load on the active elements (transistors) of the circuit is reduced as a result, and low voltage operation is possible.

[Brief description of the drawings]

Figure 1 is a conventional constant impedance circuit diagram.
Figure 2 is a constant impedance circuit diagram of this invention.
FIGS. 3 and 4 are circuit diagrams showing other embodiments of this invention. In the figure, Q ₁ , Q ₂ , and Q ₃ are transistors, R _n is a resistance for impedance matching, R _e is a bias resistance, and R _L is a load resistance.

Claims (1)

[Scope of utility model registration request] The collector and emitter of the first transistor, the matching resistor, and the second transistor are connected in order to the operating voltage source.
The collector, emitter, and bias resistor of the transistor are connected in series, a load resistor is connected to the collector of the second transistor, and inputs of opposite polarity are connected to the base of the first transistor and the base of the second transistor. Signals are simultaneously applied to obtain a desired output impedance value using the matching resistor, and the ratio between the value of the load resistor and the value of the bias resistor is determined by applying the signals to the inputs applied to the first and second transistors. 1. A constant impedance output circuit, characterized in that the constant impedance is determined in proportion to the amplitude ratio of the signal, and the signal component generated in the matching resistor is removed.