JPH03768Y2 - - Google Patents

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Publication number
JPH03768Y2
JPH03768Y2 JP1983111187U JP11118783U JPH03768Y2 JP H03768 Y2 JPH03768 Y2 JP H03768Y2 JP 1983111187 U JP1983111187 U JP 1983111187U JP 11118783 U JP11118783 U JP 11118783U JP H03768 Y2 JPH03768 Y2 JP H03768Y2
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JP
Japan
Prior art keywords
resistor
output
frequency
transistors
stereo
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Expired
Application number
JP1983111187U
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Japanese (ja)
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JPS6019261U (en
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Priority to JP1983111187U priority Critical patent/JPS6019261U/en
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Description

【考案の詳細な説明】 産業上の利用分野 本考案は、FMステレオ受信機のようなステレ
オ受信機の特に音声出力信号のノイズを軽減する
回路に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a circuit for reducing noise in a stereo receiver, particularly an audio output signal, such as an FM stereo receiver.

背景技術とその問題点 例えばFM受信機では、入力電界が弱くなると
音声出力信号のS/Nが急激に劣化する。そのた
め、入力電界が急変動する移動受信のような場合
には、音声出力信号の品位の低下が著しい。ま
た、ステレオ受信機でのステレオ時には、モノラ
ル時に比べてノイズレベルが著しく増大する。そ
こで、ステレオ受信機において、信号電界強度が
低下したときに左右の音声出力信号の高域成分を
遮断してノイズレベルを抑圧したり、ステレオ楠
に左右の音声出力信号の高域成分を混合して同相
のノイズ成分を打ち消すことにより、ノイズを較
減することが要求される。
Background Art and Its Problems For example, in an FM receiver, when the input electric field becomes weak, the S/N of the audio output signal deteriorates rapidly. Therefore, in cases such as mobile reception where the input electric field fluctuates rapidly, the quality of the audio output signal is significantly degraded. Furthermore, when a stereo receiver uses stereo, the noise level increases significantly compared to when monaural. Therefore, in a stereo receiver, when the signal electric field strength decreases, the high frequency components of the left and right audio output signals are cut off to suppress the noise level, or the high frequency components of the left and right audio output signals are mixed in the stereo receiver. It is required to calibrate the noise by canceling the in-phase noise components.

考案の目的 本考案は、この点に鑑み、簡単な回路によつ
て、1個の制御電圧源により左右の音声出力信号
の高域遮断特性と高域混合特性を同時かつ連続的
に変化させることができるようにして、入力電界
が弱いときやステレオ時のノイズを軽減すること
ができるようにしたものである。
Purpose of the invention In view of this point, the present invention aims to simultaneously and continuously change the high-frequency cutoff characteristics and high-frequency mixing characteristics of the left and right audio output signals using a single control voltage source using a simple circuit. This makes it possible to reduce noise when the input electric field is weak or during stereo.

考案の概要 本考案では、コレクタ接地とされた第1のトラ
ンジスタのエミツタを第1の容量素子と第1の抵
抗とを介して第1の入力端子に接続するととも
に、コレクタ接地とされた第2のトランジスタの
エミツタを第2の容量素子と第2の抵抗とを介し
て第2の入力端子に接続し、第1及び第2のトラ
ンジスタの夫々のベースを第3の抵抗を介して制
御電圧源に接続し、第1の容量素子と第1の抵抗
との接続点から第1の出力端子を導出するととも
に、第2の容量素子と第2の抵抗との接続点から
第2の出力端子を導出して、第1及び第2のトラ
ンジスタのエミツタに夫々第1及び第2の抵抗よ
り大なる第4及び第5の抵抗を通じて電源電圧を
供給するようにした高域遮断混合回路をステレオ
復調回路の出力側に設けて、ステレオ復調回路の
出力の左,右の音声信号を第1及び第2の入力端
子に夫々供給し、第1及び第2の出力端子から左
右の音声出力信号を夫々取り出して、コレクタ接
地のトランジスタの出力側からみたインピーダン
スを利用して高域成分を遮断するローパスフイル
タを構成し、入力側からみたインピーダンスで高
域成分の混合量を決定するようにする。
Summary of the invention In the invention, the emitter of a first transistor whose collector is grounded is connected to a first input terminal via a first capacitive element and a first resistor, and a second transistor whose collector is grounded is connected to a first input terminal via a first capacitive element and a first resistor. The emitter of the transistor is connected to a second input terminal via a second capacitor and a second resistor, and the base of each of the first and second transistors is connected to a control voltage source via a third resistor. , the first output terminal is derived from the connection point between the first capacitive element and the first resistor, and the second output terminal is derived from the connection point between the second capacitive element and the second resistor. A stereo demodulation circuit includes a high-frequency cut-off mixing circuit which is derived and supplies a power supply voltage to the emitters of the first and second transistors through fourth and fifth resistors that are larger than the first and second resistors, respectively. is provided on the output side of the stereo demodulation circuit, supplies the left and right audio signals of the output of the stereo demodulation circuit to the first and second input terminals, respectively, and takes out the left and right audio output signals from the first and second output terminals, respectively. A low-pass filter is configured to block high-frequency components using the impedance seen from the output side of the transistor whose collector is grounded, and the mixing amount of the high-frequency components is determined by the impedance seen from the input side.

実施例 第1図は本考案のステレオ受信機の一例で、
FMステレオ受信機の場合で、アンテナ1で受信
されたFM放送信号がフロントエンド2に供給さ
れて中間周波信号に変換され、これが中間周波増
幅回路3を通じてFM検波回路4に供給されて
FM検波され、その検波信号がステレオ復調回路
5に供給されて左,右のチヤンネルの音声信号
SL,SRが得られる。
Embodiment Figure 1 shows an example of the stereo receiver of the present invention.
In the case of an FM stereo receiver, an FM broadcast signal received by an antenna 1 is supplied to a front end 2 and converted to an intermediate frequency signal, which is supplied to an FM detection circuit 4 through an intermediate frequency amplification circuit 3.
FM detection is performed, and the detected signal is supplied to the stereo demodulation circuit 5 to generate left and right channel audio signals.
SL and SR are obtained.

本考案では、ステレオ復調回路5の出力側に特
殊な高域遮断混合回路6が設けられる。この高域
遮断混合回路6は、第1及び第2のトランジスタ
Q1及びQ2を有し、トランジスタQ1及びQ2のコレ
クタがそれぞれ交流的に接地され、トランジスタ
Q1,Q2のエミツタが第1,第2の容量素子C1
C2と第1,第2の抵抗R1,R2を介して第1,第
2の入力端子6a,6bに接続され、ベースが第
3の抵抗R3を介して制御端子6cに接続され、
第1,第2の容量素子C1,C2と第1,第2の抵
抗R1,R2の接続点より第1,第2の出力端子6
d,6eが導出され、トランジスタQ1,Q2のエ
ミツタが抵抗R5,R6を介してバイアス端子6f
に接続されたもので、ステレオ復調回路5の出力
の信号SL,SRが入力端子6a,6bに供給され、
制御端子6cに制御電圧VCの電圧源7が接続さ
れ、バイアス端子6fに電源電圧VBが与えられ
る。容量素子C1及びC2はそれぞれ2〜3kHz以上
の周波数に対して低インピーダンスを呈するもの
にされる。抵抗R5及びR6は充分大きくされる。
In the present invention, a special high frequency cutoff mixing circuit 6 is provided on the output side of the stereo demodulation circuit 5. This high-frequency cutoff mixing circuit 6 includes first and second transistors.
Q 1 and Q 2 , the collectors of transistors Q 1 and Q 2 are respectively grounded AC, and the transistor
The emitters of Q 1 and Q 2 are the first and second capacitive elements C 1 ,
C2 and the first and second input terminals 6a and 6b via the first and second resistors R1 and R2 , and the base is connected to the control terminal 6c via the third resistor R3. ,
The first and second output terminals 6 are connected to the connection point between the first and second capacitive elements C 1 and C 2 and the first and second resistors R 1 and R 2 .
d and 6e are derived, and the emitters of transistors Q 1 and Q 2 are connected to bias terminal 6f via resistors R 5 and R 6 .
The output signals S L and S R of the stereo demodulation circuit 5 are supplied to the input terminals 6 a and 6 b,
A voltage source 7 of a control voltage V C is connected to the control terminal 6c, and a power supply voltage V B is applied to the bias terminal 6f. Each of the capacitive elements C 1 and C 2 is made to exhibit low impedance at frequencies of 2 to 3 kHz or higher. Resistors R 5 and R 6 are made sufficiently large.

この高域遮断混合回路6で、容量素子C1,C2
のインピーダンスをXC1,XC2、トランジスタQ1
Q2のエミツタ抵抗をre1,re2、ベース抵抗をrb1
rb2、ベース電圧をVb1,Vb2、相互コンダクタン
スをgn1,gn2、出力アドミツタンスをgp1,gp2
すると、信号SL及びSRがトランジスタQ1,Q2
接合容量や帰還容量などを無視できるような周波
数の場合には、この回路6は等価的に第2図のよ
うに表わされ、電圧VB及びVCによるバイアスが
トランジスタQ1,Q2を遮断領域にするときは、
出力端子6d,6eと接地との間のインピーダン
スが抵抗R1,R2に比べて著しく大きく、出力端
子6d,6eには信号SL,SRそのものがもとのま
まのレベルで現われる。
In this high-frequency cutoff mixed circuit 6, capacitive elements C 1 and C 2
The impedance of X C1 , X C2 , transistor Q 1 ,
The emitter resistance of Q 2 is r e1 , r e2 , the base resistance is r b1 ,
r b2 , the base voltages are V b1 , V b2 , the mutual conductances are g n1 , g n2 , and the output admittances are g p1 , g p2 , the signals S L and SR are the junction capacitances and feedback of transistors Q 1 and Q 2 In the case of a frequency where capacitance etc. can be ignored, this circuit 6 is equivalently represented as shown in Fig. 2, and the bias by voltages V B and V C brings transistors Q 1 and Q 2 into the cut-off region. when,
The impedance between the output terminals 6d, 6e and the ground is significantly larger than that of the resistors R1 , R2 , and the signals S L , S R themselves appear at the original levels at the output terminals 6d, 6e.

そして、制御電圧VCを下げてトランジスタQ1
Q2を動作領域にすると、出力端子6d,6eに
現われる信号SL,SRの成分Sd(SL),Se(SR)は、
トランジスタQ1,Q2のコレクタ接地小信号電流
増幅率をhfc1,hfc2とすると、 Sd(SL)=XC1+re1+{1/gp1rb1+R3〔rb2+h
fc2{1/gp2(re2+XC2+R2)}〕)/hfc1}/R1
XC1re1+{1/gp1rb1+R3〔rb2+hfc2{1/gp2
(re2+XC2+R2)}〕)/hfc1}SL Se(SR)=XC2re2+{1/gp1rb2+(R3〔rb1+h
fc1{1/gp1(re1+XC1+R1)}〕)/hfc2}/R2
XC2+re2{1/gp1rb2+(R3〔rb1+hfc1{1/gp1
(re1+XC1+R1)}〕)/hfc2}SR となる。また、C点に現われる信号SL,SRの成分
をSC(SL),SC(SR)とすると、 SC(SL)=1/gp1rb1+(R3〔rb2+hfc2{1/g
p2(re2+XC2+R2)}〕)/hfc1/XC1+re1+{1/
gp1rb1+(R3〔rb2+hfc2{1/gp2(re2+XC2
R2)}〕)/hfc1} ×R3〔rb2+hfc2{1/gp2(re2+XC2+R2)}〕
/rb1+(R3〔rb2+hfc2{1/gp2(re2+XC2R2
}〕)×Sd(SL) SC(SR)=1/gp2rb2+(R3〔rb1+hfc1{1/g
p1(re1+XC1+R1)}〕)/hfc2/XC2+re2+{1/
gp2rb2+(R3〔rb1+hfc1{1/gp1(re1+XC1
R1)}〕)/hfc2} ×R3〔rb1+hfc1{1/gp1{re1+XC1R1)}〕/
rb2+(R3〔rb1+hfc1{1/gp1(re1+XC1+R1
}〕)×Se(SR) となり、出力端子6d,6eに逆に信号SR,SL
成分も Sd(SR)=hfc1{1/gp1(re1+XC1+R1)}/rb1
+hfc1{1/oo1(re1+XC1+R1)}×R1/R1+XC1
re1×SC(SR) Se(SL)=hfc2{1/gp2(re2+XC2+R2)}/rb2
+hfc2{1/gp2(re2XC2+R2)}×R2/R2+XC2+re
2
×SC(SL) で表わされる分だけ現われる。
Then, the control voltage V C is lowered and the transistor Q 1 ,
When Q 2 is set as the operating region, the components S d (S L ) and Se (S R ) of the signals S L and S R appearing at the output terminals 6d and 6e are as follows.
If the common collector small signal current amplification factors of transistors Q 1 and Q 2 are h fc1 and h fc2 , then S d (S L ) = X C1 + r e1 + {1/g p1 r b1 + R 3 [r b2 + h
fc2 {1/g p2 (r e2 +X C2 +R 2 )}])/h fc1 }/R 1 +
X C1 r e1 +{1/g p1 r b1 +R 3 [r b2 +h fc2 {1/g p2
(r e2 +X C2 + R 2 ) } ] ) / h fc1 } S L S e (S R ) =
fc1 {1/g p1 (r e1 +X C1 +R 1 )}])/h fc2 }/R 2 +
X C2 +r e2 {1/g p1 r b2 +(R 3 [r b1 +h fc1 {1/g p1
(r e1 +X C1 +R 1 )})/h fc2 }S R. Furthermore, if the components of the signals S L and S R appearing at point C are S C (S L ) and S C (S R ), then S C (S L )=1/g p1 r b1 + (R 3 [r b2 +h fc2 {1/g
p2 (r e2 +X C2 +R 2 )})/h fc1 /X C1 +r e1 +{1/
g p1 r b1 + (R 3 [r b2 +h fc2 {1/g p2 (r e2 +X C2 +
R 2 )})/h fc1 } ×R 3 [r b2 +h fc2 {1/g p2 (r e2 +X C2 +R 2 )}]
/r b1 + (R 3 [r b2 +h fc2 {1/g p2 (r e2 +X C2 R 2 )
})×S d (S L ) S C (S R )=1/g p2 r b2 + (R 3 [r b1 +h fc1 {1/g
p1 (r e1 +X C1 +R 1 )})/h fc2 /X C2 +r e2 +{1/
g p2 r b2 + (R 3 [r b1 +h fc1 {1/g p1 (r e1 +X C1 +
R 1 )}])/h fc2 } ×R 3 [r b1 +h fc1 {1/g p1 {r e1 +X C1 R 1 )}]/
r b2 + (R 3 [r b1 + h fc1 {1/g p1 (r e1 +X C1 +R 1 )
})×S e (S R ), and conversely the components of the signals S R and S L at the output terminals 6d and 6e are also S d (S R )=h fc1 {1/g p1 (r e1 +X C1 +R 1 )}/r b1
+h fc1 {1/o o1 (r e1 +X C1 +R 1 )}×R 1 /R 1 +X C1 +
r e1 ×S C (S R ) S e (S L )=h fc2 {1/g p2 (r e2 +X C2 +R 2 )}/r b2
+h fc2 {1/g p2 (r e2 X C2 +R 2 )}×R 2 /R 2 +X C2 +r e
2
×S C (S L ) appears.

従つて結局、出力端子6dには、SL′=Sd(SL
+Sd(SR)で表わされる、信号SLがローパスフイ
ルタを通じて高域成分が遮断されたものと信号SR
の高域成分が混合された信号が得られ、出力端子
6eには、SR′=Se(SR)+Se(SL)で表わされる、
信号SRがローパスフイルタを通じて高域成分が遮
断されたものと信号SLの高域成分が混合された信
号が得られる。そして、制御電圧VCを変化させ
てエミツタ抵抗re1,re2などのパラメーターを変
化させることにより、出力端子6d,6eでの信
号SL,SRの高域遮断特性と信号SR,SLの高域混合
特性が連続的に変えられ、制御電圧VCを低くす
るほど、出力端子6d,6eでの信号SL,SRの高
域成分の遮断量と信号SR,SLの高域成分の混合量
が増加する。
Therefore, in the end, the output terminal 6d has S L ′=S d (S L )
+S d (S R ), the signal S L passes through a low-pass filter with its high-frequency components cut off, and the signal S R
A signal with mixed high - frequency components of
A signal is obtained in which the high-frequency components of the signal S R are filtered through a low-pass filter and the high-frequency components of the signal S L are mixed. By changing parameters such as the emitter resistances r e1 and r e2 by changing the control voltage V C , the high-frequency cutoff characteristics of the signals S L and S R at the output terminals 6d and 6e and the signals S R and S The high - frequency mixing characteristics of L are continuously changed , and the lower the control voltage V The amount of high frequency component mixed increases.

従つて、信号電界強度が低下したときに制御電
圧VCを下げれば、そのチヤンネルの音声信号SL
SRの高域成分が遮断されてノイズレベルが抑制さ
れると同時に、他チヤンネルの音声信号SR,SL
高域成分が混合されて左右のチヤンネルの同相の
ノイズ成分が打ち消されるので、ノイズを軽減で
きる。
Therefore, if the control voltage V C is lowered when the signal field strength decreases, the audio signals S L ,
At the same time, the high-frequency components of S R are blocked and the noise level is suppressed, and at the same time, the high-frequency components of the audio signals S R and S L of other channels are mixed, canceling out the in-phase noise components of the left and right channels. Can reduce noise.

実際には、制御電圧VCが信号電界強度に応じ
て自動的に変化して、高域遮断特性と高域混合特
性が自動的に変えられるようにするとよい。第3
図はその場合の例で、中間周波増幅回路3を通じ
た中間周波信号が振幅検波回路8に供給されて振
幅検波されることにより信号電界強度に比例した
検波電圧が得られ、これが前述の制御電圧VC
して高域遮断混合回路6の制御端子6cに与えら
れる。従つて、信号電界強度が低下するにつれ
て、そのチヤンネルの音声信号SL,SRの高域成分
の遮断量が増加して信号電界強度の低下とともに
増大するノイズレベルが抑えられるとともに、他
のチヤンネルの音声信号SR,SLの高域成分の混合
量が増加して左右のチヤンネルの同相のノイズ成
分が打ち消されるようになり、ノイズが軽減す
る。
In practice, it is preferable that the control voltage V C be automatically changed according to the signal electric field strength so that the high-frequency cutoff characteristics and the high-frequency mixing characteristics can be automatically changed. Third
The figure shows an example of such a case, in which the intermediate frequency signal passed through the intermediate frequency amplifier circuit 3 is supplied to the amplitude detection circuit 8 and amplitude detected, thereby obtaining a detected voltage proportional to the signal electric field strength, which is then applied to the control voltage described above. It is applied as V C to the control terminal 6c of the high frequency cutoff mixing circuit 6. Therefore, as the signal electric field strength decreases, the amount of blocking of the high-frequency components of the audio signals S L and S R of that channel increases, suppressing the noise level that increases with the decrease of the signal electric field strength, and blocking the high frequency components of the audio signals S L and S R of that channel. The amount of mixing of the high-frequency components of the audio signals S R and S L increases, and the in-phase noise components of the left and right channels are canceled out, and the noise is reduced.

第4図は上述の高域遮断混合回路6を2段接続
した高域遮断特性の一例、第5図は同じく高域混
合特性の一例で、高域混合特性はステレオ時の分
離度で表わしている。パラメーターの制御電圧
VCはV1>V2>V3>V4>V5>V6>V7の関係にあ
る。
Fig. 4 shows an example of the high-frequency cutoff characteristic when the above-mentioned high-frequency cutoff mixing circuit 6 is connected in two stages, and Fig. 5 shows an example of the high-frequency mixing characteristic.The high-frequency mixing characteristic is expressed by the degree of separation in stereo. There is. Parameter control voltage
V C has the relationship of V 1 > V 2 > V 3 > V 4 > V 5 > V 6 > V 7 .

考案の効果 本考案のステレオ受信機によれば、コレクタ接
地とされた第1のトランジスタQ1のエミツタを
第1の容量素子C1と第1の抵抗R1とを介して第
1の入力端子6aに接続するとともに、コレクタ
接地とされた第2のトランジスタQ2のエミツタ
を第2の容量素子C2と第2の抵抗R2とを介して
第2の入力端子6bに接続し、第1及び第2のト
ランジスタQ1及びQ2の夫々のベースを第3の抵
抗R3を介して制御電圧Vcの電圧源に接続し、第
1の容量素子C1と第1の抵抗R1との接続点から
第1の出力端子6dを導出するとともに、第2の
容量素子C2と第2の抵抗R2との接続点から第2
の出力端子6eを導出して、第1及び第2のトラ
ンジスタQ1及びQ2のエミツタに夫々第1及び第
2の抵抗R1及びR2より大なる第4及び第5の低
抗R5及びR6を通じて電源電圧を供給するように
した高域遮断混合回路をステレオ復調回路5の出
力側に設けて、ステレオ復調回路5からの左右の
音声信号SL及びSRを第1及び第2の入力端子6a
及び6bに夫々供給し、第1及び第2の出力端子
6d及び6eから左右の音声出力信号を取り出し
て、コレクタ接地とされた第1及び第2のトラン
ジスタQ1及びQ2の出力側、即ち、エミツタ側か
らみたインピーダンスを利用して高域成分を遮断
するローパスフイルタを構成し、入力側、即ち、
ベース側からみたインピーダンスで高域成分の混
合量を決定するようにしたので、1個の制御電圧
源により左右の音声出力信号の高域遮断特性と高
域混合特性を同時かつ連続的に変化させることが
でき、入力電界が弱いときやステレオ時のノイズ
を軽減することができる。従つて、特に入力電界
が急変動する移動受信のような場合における聴感
上の性能が著しく向上する。
Effects of the Invention According to the stereo receiver of the present invention, the emitter of the first transistor Q1 whose collector is grounded is connected to the first input terminal 6a via the first capacitive element C1 and the first resistor R1. At the same time, the emitter of the second transistor Q 2 whose collector is grounded is connected to the second input terminal 6b via the second capacitive element C 2 and the second resistor R 2 . The bases of the second transistors Q 1 and Q 2 are connected to the voltage source of the control voltage Vc via the third resistor R 3 , and the first capacitive element C 1 and the first resistor R 1 are connected to each other. The first output terminal 6d is derived from the point, and the second output terminal 6d is derived from the connection point between the second capacitive element C2 and the second resistor R2 .
The output terminal 6e of the transistor Q 1 and the emitter of the second transistor Q 2 are connected to fourth and fifth low resistors R 5 which are larger than the first and second resistors R 1 and R 2 , respectively. A high-frequency cut-off mixing circuit that supplies the power supply voltage through R6 and R6 is provided on the output side of the stereo demodulation circuit 5, and the left and right audio signals S L and S R from the stereo demodulation circuit 5 are connected to the first and second input terminal 6a of
and 6b, respectively, and take out the left and right audio output signals from the first and second output terminals 6d and 6e, and the output sides of the first and second transistors Q1 and Q2 whose collectors are grounded, i.e. , constitute a low-pass filter that blocks high-frequency components using the impedance seen from the emitter side, and the input side, that is,
Since the amount of high-frequency component mixing is determined by the impedance seen from the base side, the high-frequency cutoff characteristics and high-frequency mixing characteristics of the left and right audio output signals can be changed simultaneously and continuously using a single control voltage source. This makes it possible to reduce noise when the input electric field is weak or during stereo. Therefore, the auditory performance is significantly improved, especially in cases such as mobile reception where the input electric field changes rapidly.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のステレオ受信機の一例の接続
図、第2図はその要部の高域遮断混合回路の等価
回路を示す図、第3図は本考案のステレオ受信機
の他の例の接続図、第4図及び第5図は本考案の
ステレオ受信機における高域遮断特性及び高域混
合特性の一例を示す特性曲線図である。 図中、5はステレオ復調回路、6は高域遮断混
合回路、Q1及びQ2は第1及び第2のトランジス
タ、C1及びC2は第1及び第2の容量素子、R1
R2及びR3は第1,第2及び第3の抵抗、6a及
び6bは第1及び第2の入力端子、6d及び6e
は第1及び第2の出力端子、7は制御電圧源であ
る。
Fig. 1 is a connection diagram of an example of the stereo receiver of the present invention, Fig. 2 is a diagram showing an equivalent circuit of the main part of the high-frequency cutoff mixing circuit, and Fig. 3 is another example of the stereo receiver of the present invention. The connection diagram, FIGS. 4 and 5 are characteristic curve diagrams showing an example of high frequency cutoff characteristics and high frequency mixing characteristics in the stereo receiver of the present invention. In the figure, 5 is a stereo demodulation circuit, 6 is a high frequency cutoff mixing circuit, Q 1 and Q 2 are first and second transistors, C 1 and C 2 are first and second capacitive elements, R 1 ,
R 2 and R 3 are the first, second and third resistors, 6a and 6b are the first and second input terminals, 6d and 6e
are first and second output terminals, and 7 is a control voltage source.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1及び第2のトランジスタの夫々のコレクタ
が交流的に接地され、上記第1のトランジスタの
エミツタが第1の容量素子と第1の抵抗とを介し
て第1の入力端子に接続されるとともに、上記第
2のトランジスタのエミツタが第2の容量素子と
第2の抵抗とを介して第2の入力端子に接続さ
れ、上記第1及び第2のトランジスタの夫々のベ
ースが第3の抵抗を介して制御電圧源に接続さ
れ、上記第1の容量素子と上記第1の抵抗との接
続点から第1の出力端子が導出されるとともに、
上記第2の容量素子と上記第2の抵抗との接続点
から第2の出力端子が導出され、上記第1及び第
2のトランジスタのエミツタに夫々上記第1及び
第2の抵抗より大なる第4及び第5の抵抗を通じ
て電源電圧が供給されるものとされた高域遮断混
合回路が、ステレオ復調回路の出力側に設けら
れ、上記ステレオ復調回路からの左右の音声信号
が夫々上記第1及び第2の入力端子に供給され、
上記第1及び第2の出力端子から夫々左右の音声
出力信号が取り出されるステレオ受信機。
The collectors of each of the first and second transistors are AC grounded, and the emitter of the first transistor is connected to a first input terminal via a first capacitor and a first resistor. , an emitter of the second transistor is connected to a second input terminal via a second capacitor and a second resistor, and a base of each of the first and second transistors connects to a third resistor. A first output terminal is connected to a control voltage source via a control voltage source, and a first output terminal is derived from a connection point between the first capacitive element and the first resistor;
A second output terminal is led out from a connection point between the second capacitive element and the second resistor, and a second output terminal is connected to the emitters of the first and second transistors, respectively. A high-frequency cutoff mixing circuit to which the power supply voltage is supplied through the fourth and fifth resistors is provided on the output side of the stereo demodulation circuit, and the left and right audio signals from the stereo demodulation circuit are connected to the first and fifth resistors, respectively. supplied to a second input terminal;
A stereo receiver from which left and right audio output signals are respectively taken out from the first and second output terminals.
JP1983111187U 1983-07-18 1983-07-18 stereo receiver Granted JPS6019261U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983111187U JPS6019261U (en) 1983-07-18 1983-07-18 stereo receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983111187U JPS6019261U (en) 1983-07-18 1983-07-18 stereo receiver

Publications (2)

Publication Number Publication Date
JPS6019261U JPS6019261U (en) 1985-02-09
JPH03768Y2 true JPH03768Y2 (en) 1991-01-11

Family

ID=30258278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983111187U Granted JPS6019261U (en) 1983-07-18 1983-07-18 stereo receiver

Country Status (1)

Country Link
JP (1) JPS6019261U (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55121548U (en) * 1979-02-22 1980-08-28

Also Published As

Publication number Publication date
JPS6019261U (en) 1985-02-09

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