JPS6238364Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a muting circuit for an FM stereo receiver using a switching method.

Generally, in audio circuits, a method is adopted in which a field effect transistor or a large capacitance capacitor is added to the signal transmission system, and audio output is interrupted by a muting signal. In this way, conventional muting circuits are formed by adding the above-mentioned elements to the outside of a semiconductor integrated circuit, and although they can be easily constructed, the number of components increases, making FM stereo receivers expensive. There are certain drawbacks.

The purpose of the muting circuit of the present invention is to provide a muting circuit suitable for a switching type FM stereo receiver.

Another object is to provide a muting circuit suitable for semiconductor integrated circuit implementation.

Another object of the present invention is to provide a muting circuit that suppresses pop noise during a muting operation.

Still another object is to provide an inexpensive FM stereo receiver by forming a muting circuit with fewer elements.

The muting circuit of the present invention was designed to achieve the above-mentioned objectives, and is suitable for a switching type FM stereo receiver. In a switching type FM stereo receiver, the chopper circuit is cut off during monaural reception, and the 38KHz switching signal is input to the chopper circuit during stereo reception, and the composite signal is time-divided. On the other hand, when the input signal level reaches the muting operation level, two transistors forming the chopper circuit are simultaneously activated to cut off the composite signal and perform muting.

Hereinafter, the muting circuit of the present invention will be explained based on FIGS. 1 and 2.

FIG. 1 shows an embodiment of a switching type FM stereo receiver equipped with a muting circuit according to the present invention. The FM stereo signal input from the antenna 1 is input to the front end 2, where it undergoes processing such as input signal selection and amplification, and is input to the intermediate frequency amplification circuit 3. The intermediate frequency amplification circuit 3 performs signal processing such as selection, amplification, and amplitude limitation of a desired signal. This signal is then input to the FM detection circuit 4. The FM detection circuit 4 detects frequency deviation from the center frequency of 10.7MHz, and extracts a composite signal from the high frequency signal. This composite signal is input through a coupling capacitor C to an adder circuit 10 having a chopper circuit 8 between its input terminals, and is also input to a demodulation signal generating circuit 5.

The demodulation signal generation circuit 5 is a circuit that generates a 38KHz demodulation signal from the synchronization signal of the 19KHz pilot signal, and a 38KHz signal whose phase is inverted to each other is applied to the bases of the transistors Q ₁ and Q ₂ forming the chopper circuit 8 via the drive circuit 6. A switching signal is input. 11 and 12 are output terminals.

The muting circuit system, which is the main part of the present invention, inputs the output from the intermediate frequency amplifier circuit 3 to the muting level detection circuit 9 to obtain a DC output according to the input signal level, and also mutates the level of the DC output. Compare and detect the level and generate a muting signal and supply it to the drive circuit 6
This circuit system suppresses the supply of the Hz switching signal to the chopper circuit 8.

Now, the configuration of each part will be explained based on FIGS. 1 and 2.

The chopper circuit 8 is composed of PNP transistors Q ₁ and Q ₂ , and the emitters of the PNP transistors Q ₁ and Q ₂ are commonly connected and connected to the DC voltage source 7 .
The collector of PNP transistor Q ₁ is connected to the connection point of resistors R ₁ and R ₃ , and the collector of PNP transistor Q ₂ is connected to the connection point of resistors R ₂ and R ₄ .
Further, the other ends of resistors R ₁ and R ₂ are commonly connected to a coupling capacitor C. and,
The other ends of resistors R ₃ and R ₄ are connected to transistors Q _{5 and} R 4 , respectively.
Connected to the base of Q ₆ . Addition circuit 10
Transistors Q ₅ and Q ₆ constitute a differential amplifier, load resistors R _L are connected to the collectors of transistors Q ₅ and Q ₆ , respectively, and emitter resistors R _{5 and} R are connected to the emitters of transistors Q 5 and Q ₆ , respectively. ₆ is connected, and the other end is commonly connected and grounded via resistor _R7 .

Next, the configuration of the drive circuit 6 will be explained using the embodiment shown in FIG. A constant current source ₁₆ is connected to the commonly connected emitters of transistors Q ₁₀ and Q ₁₁ that receive a 38KHz switching signal.
Resistors R ₁₁ and R ₁₂ are connected to the collector of Q ₁₁ , and the other end is grounded. One ends of resistors R ₁₁ and R ₁₂ are connected to the bases of transistors Q ₁₂ and Q ₁₃ , respectively,
Resistors R ₉ and R ₁₀ are connected to the collectors of transistors Q ₁₂ and Q _13.
is connected. And transistors Q ₁₂ , Q ₁₃
The emitter is grounded. Further, a DC voltage source 15 is connected between the common connection point of the resistors R ₉ and R ₁₀ and the ground. A resistor _R13 is connected to a connection point a between the resistor _R9 and the collector of the transistor _Q12 , and the other end is connected to the base of the transistor _Q2 . In addition, a resistor is connected to the connection point b between the resistor _R10 and the collector of the transistor _Q13 .
_R14 is connected and the other end is connected to the base of transistor _Q1 .

Now, I will explain the muting circuit system. A demodulation signal generation circuit 5 comprising a PLL (Phase-Locked Loop) circuit or the like detects the 19KHz pilot signal and further multiplies it to obtain a 38KHz switching signal, which is supplied to the chopper circuit 8 via the drive circuit 6. The drive circuit 6 is controlled by a muting level detection circuit 9. The DC output corresponding to the input signal level obtained by the rectifying and smoothing circuit 13 included in the muting level detection circuit 9 is compared and detected with a predetermined muting level, and when the level of the DC output exceeds the muting level, a muting signal is detected. The signal is generated, and the drive circuit 6 is controlled to apply muting to the signal transmission system.

Below, a circuit equipped with the mutating circuit of the present invention will be described.
The operation of the FM stereo receiver will be explained based on FIGS. 1 and 2. During stereo reception, 38KHz switching signals with mutually inverted phases are input to the bases of the transistors Q ₁₀ and Q ₁₁ of the drive circuit 6, and the transistors Q ₁₀ and Q ₁₁ alternately repeat active and cut-off states. transistor at the same time
Similarly, Q ₁₂ and Q ₁₃ are also alternately active and blocked. When transistor Q ₁₀ is on, transistor Q ₁₁ is off. If the transistor Q ₁₂ is on, the potential at point a on the collector side of the transistor Q ₁₂ becomes a low level, and the transistor Q ₂ of the chopper circuit 8 becomes on. On the other hand, since the transistor _Q11 is in the off state, the transistor _Q13 is also turned off and its collector potential becomes high level. Therefore, the transistor _Q1 of the chopper circuit 8 is turned off. In this way, the transistors Q ₁ and Q ₂ of the chopper circuit 8 are alternately activated and disconnected, and the stereo decomposed signal is time-divisionally divided to perform stereo separation. Incidentally, during monaural reception, the potential of the commonly connected emitters of transistors Q ₁₀ and Q ₁₁ is changed to the stereo/monaural switching signal A.
, and the transistor Q ₁₀ ,
Set Q ₁₁ to the cut-off state. The potentials at point a and point b both become high level, and the transistor of chopper circuit 8
Q ₁ and Q ₂ are cut off. In this way, the supply of the 38KHz switching signal to the chopper circuit 8 is cut off, resulting in a monaural reception state.

Next, we will explain the operation of the muting circuit system.
The input level of the FM signal is detected by a muting level detection circuit 9. The muting level detection circuit 9 rectifies and smoothes the FM signal by the rectifying and smoothing circuit 13, and when it detects that the FM signal level has reached the muting operation level, a muting signal is transmitted to the bases of transistors Q ₈ and Q ₉ . It is input and becomes active. Therefore, during the muting operation, transistors Q ₁₀ and Q ₁₁ are activated, and accordingly, a bias voltage is generated in resistors R ₁₁ and R ₁₂ , and transistors Q ₁₂ and Q ₁₃ are activated. Then, the transistors Q ₁ and Q ₂ forming the chopper circuit 8 become operational, and the 38K
The Hz switching signal is blocked. Further, since the composite signal component supplied from the coupling capacitor C is grounded in an alternating current manner by the chopper circuit 8, muting is applied to the signal transmission system. At the same time, transistors Q ₅ and Q ₆ of the adder circuit 10
A bias voltage is supplied to the base from a DC voltage source 7. Therefore, the collector potential of the transistors Q ₅ and Q ₆ , that is, the output terminals 11 and 1 of the adder circuit 10
Since the DC level of No. 2 can be maintained substantially constant, pop noise can be prevented from occurring.

Of course, the transistors Q ₁ and Q ₂ of the chopper circuit 8
is formed by a PNP transistor, but NPN
It may also be formed using a transistor. Furthermore, the load circuit of the adder circuit 10 is not limited to the resistor _RL . Furthermore, the driving circuit 6 for the 38 KHz switching signal is not limited to the circuit shown in FIG. 2, but can be implemented by various circuits. In that case, the driving circuit 6 may be controlled so that the mutating signal causes the transistors Q ₁ and Q ₂ constituting the chopper circuit 8 to be activated simultaneously.

As mentioned above, the muting circuit of the present invention makes it possible to form a muting circuit by simply adding a very small number of circuit elements to an existing switching type FM stereo receiver. Furthermore, since a muting circuit can be formed by simply adding transistors Q ₈ and Q ₉ to the base electrodes of transistors Q ₁₀ and Q ₁₁ of the drive circuit 6, it is easy to integrate the circuit into a semiconductor integrated circuit, and an inexpensive FM stereo receiver can be provided. .

Furthermore, in such a muting circuit, during the muting operation, a bias voltage is supplied to the base of the transistor constituting the adder circuit, so that fluctuations in the DC level at the output end are small and generation of pop noise can be suppressed.

As mentioned above, the muting circuit of the present invention has various excellent effects and is extremely effective.

[Brief explanation of the drawing]

Figure 1 shows the switching method FM according to the present invention.
FIG. 2 is a diagram showing an example of a stereo receiver. FIG. 2 is a circuit diagram showing an embodiment of the main parts of the muting circuit of the present invention. 1: Antenna, 2: Front end, 3: Intermediate frequency amplification circuit, 4: FM detection circuit, 5: Demodulation signal generation circuit, 6: Drive circuit, 8: Chopper circuit,
9: Mutating level detection circuit including a rectifying and smoothing circuit 13, 10: Adding circuit, 11, 12: Output terminals.

Claims (1)

[Scope of utility model registration request] An adder circuit consisting of a differential amplifier in which an emitter resistor is connected to the emitters of a pair of transistors and the other ends thereof are connected in common, and a chopper circuit made of a pair of transistors is provided between the input terminals of the adder circuit, and each of the chopper circuits In a switching type FM stereo receiver that separates a composite signal by inputting 38KHz subcarrier signals with mutually inverted phases to the base of a transistor, when the received signal level reaches the muting level, the chopper circuit is activated. A muting circuit for an FM stereo receiver characterized by mutating a signal transmission system by activating two transistors at the same time.