JPS5985154A - Synchronization separating circuit of digital signal - Google Patents

Abstract

PURPOSE:To protect dropout and to prevent malfunction by feeding back an output of a counter controlled by a synchronizing pattern to an input side and deciding the phase of the synchronizing pattern by a jitter compensation window generator operated by said output. CONSTITUTION:When a serial digital signal is inputted to a terminal T1, a synchronizing pattern detecting gate 2 detects the synchronizing pattern via a serial/parallel converter 1. A counter 3A is controlled by the synchronizing pattern, the output is fed back to the input side of the counter and inputted to the jitter compensating window generator 9. Since no output is obtained if the next synchronizing pattern is not fed to the window generated after about 1 frame from the synchronizing pattern at the jitter compensation window generator 9, no output is obtained even if the same pattern as the synchronizing pattern is generated intermediately. Since the output of the counter is fed back, the output is reset at each frame and the dropout is protected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention detects synchronization patterns included in a digital signal at a nearly constant period (in this specification, one period is referred to as one frame) and separates them. This invention relates to a synchronization separation circuit for digital signals.

Conventionally, a circuit having the configuration shown in FIG. 1 has been known as a circuit for this expansion. In the figure, 1 constitutes a synchronous pattern detector 'clt', a serial-to-parallel converter that converts serial data input to terminal '1'1 into parallel data, and 2Q's 1ml terminal 'I'. There is a synchronization pattern detection game that detects the same pattern as the synchronization pattern contained in the serial digital signal entered manually in "1". 6G is a counter that is controlled by the 1 synchronization pulse generated by the above synchronous pattern detection gate 2, and 4 is a 1j latch for determining the timing for removing the synchronous pattern.

5 is a frame synchronization signal generation gate (OJ+, consisting of a gate) which generates all frame synchronization signals according to the signal from the counter 6, and 6 is the signal from the synchronization pattern separation latch 4 and the terminal 'J'. A synchronization pattern separation game (ANi
) is made up of gate □).

Next, the operation of the synchronization separation circuit having the above structure will be explained with reference to the timing chart shown in FIG. 2 as appropriate.

A serial digital signal supplied to the terminal 'J'1 and containing a synchronization pattern l) k as shown in FIG. The pattern' detection gate 2 detects only the pattern 7 which is the same as the above synchronization pattern I), and generates the synchronization pulse a shown in FIG. 2(2) at its output. The counter 3 is initially in a dog state where the same jυ' is not achieved, and the shift 1 is the u' force of the synchronous pattern separation gate 2.
It is cleared by the JIIJ pulse a, and generates a time axis based on the synchronization pulse ai, as shown in FIG. 2 (3). The phase of the synchronous Bakun minute Pint latch 4 and Freno signal generation gate 5 is determined by the time +[11I output from the color/receiver 6 described above. From the above synchronization pattern separation latch 4,
) is obtained, and this output (construction synchronization pattern Fj
It is supplied to the lA gate 6. The synchronization pattern separation gate 6 receives the output shown in FIG. 2 (4) from the synchronization pattern separation latch 4 and the output shown in FIG.
) is supplied with a serial digital signal containing the same butter/P as shown in FIG.
The signal shown in Figure 2 (6) is sent to terminal '1
It is output to 2. First, the frame synchronization signal shown in FIG. 2 (5) is output from the frame synchronization signal generation gate 5 to the terminal '1'3.

The above 1 is a conventional synchronous component consisting of [゛11 circuit, the same J pulse a (82
(See Figure 2 (1)) is lost, the same pattern as the synchronization pattern P (see Figure 2 (1)) is generated in the digital signal. In this case, the time axis of the output from the counter deviates from the time axis due to the normal synchronization pulse, and it becomes erroneously synchronized, and the phase of the output from the synchronization pattern separation latch 4 and the frame synchronization signal generation gate 5 is disturbed. Therefore, if normal synchronization separation cannot be performed, there will be one drawback.

The present invention has been made in order to eliminate all of the above-mentioned drawbacks of the conventional art, and has a circuit configuration in which the first and second counters are arranged. Even in this case, if a dropout protection function is provided in which one frame synchronization signal is output for each frame, the pattern is the same as the internuclear 1υ pattern that is included in the digital signal other than the synchronization pattern. 1. Prevent incorrect synchronization by ignoring this even if it occurs. IL1 is committed to providing all digital signal synchronous separation circuits.

Hereinafter, an embodiment of the synchronous component 1';li circuit according to the present invention will be described. In the circuit configuration diagram shown in FIG. 6, the same part as shown in FIG.
The detailed explanation will be omitted.

In FIG. 3, 1 is a serial-to-parallel converter, 2 is a Jv'' pattern detection gate, 3Δ is a first counter,
4 is 1 jli latch for synchronization pattern, 5 is 1 frame same
6 is a synchronous pattern separation gate. Furthermore, the parts added as part 1 of the present invention are as follows. a second dropout protection gate 7.8, a jitter correction window generator 9 which is set by a shift register, a second counter 10 which is set to 1 by the output of the second dropout protection gate 8; ．． This is gate 11.

Next, let's move on to the synchronization according to the present invention, which consists of the above-mentioned one configuration! l [Circuit (7) Q'il 11: will be explained with reference to the timing charts shown in FIGS. 4, 5, and 6 as appropriate.

The above-mentioned first counter 6A uses the synchronization pulse a as a reference from the state where the synchronization is not achieved. In addition, a feedback pulse having the same phase as the synchronizing pulse a shown in FIG. 4(1) is fed back to the gl dropout protection gate 7 every frame period.-i 7C1 The time axis in the output of the 10th counter 6A is determined by the jitter correction window (which determines the phase of the earthenware 9). A window C shown in FIG. 4 (2) is generated near the position where OI (OI) is generated. The above-mentioned window C (see FIG. 4 (2)) from the window generator 9 is supplied, and the above-mentioned synchronous cross a
is the above window (
If there is no one inside, as shown in Figure 4 (3), ignore the synchronizing pulse a of 1 random j [~, the above synchronizing pulse a enters the above evil Only when the synchronization pulse is active, a synchronizing pulse di is applied to its output as shown in FIG. 5 (13). I6. Also in FIG. 5, (1) shows the synchronizing pulse a, and t2) shows the window.

- the second counter 10 receives the synchronizing pulse d and a feedback pulse having the same phase as the synchronizing pulse d, which is applied by the second dropout protection gate 1.8;
(see Figure (4) and Figure 5 (4)),
A time axis based on the pulse e described above is generated in the output, and during this time +h causes the synchronization pattern separation launch 4
1) and the phase of the output in frame synchronization signal generator +-5 are determined. Incidentally, the synchronous pattern separation cage 6 whose bottom is formed by an ANI gate is exactly the same as the one explained in the conventional example.

In the disclosed separation circuit according to the present invention comprising the above-mentioned groove bottom, if a pattern identical to the synchronization pattern is generated in the digital signal from which the synchronization pattern has been separated, and the hexagonal pattern is generated, the serial-parallel converter 1 and the same, \υ'' pattern detection gate 2 is configured with ti'I, and one synchronous pattern detector is
A synchronizing pulse a"'tR as shown in FIG. It becomes a synchronous state, but at this time the same jυ as above
'' Pulse a' does not fall within the window C generated by the Sissocou correction window generator 9 as shown in FIG. As shown in 3), the synchronizing pulse d is not generated. At this time, the output of the second dropout protection gate 8 is as shown in FIG.
A pulse e shown in 4) is generated. Therefore, the time axis in the second counter 10 remains in a synchronized state, and a signal is output to the terminal J2 via the synchronization pattern separation latch 4 and the synchronization pattern separation gate 6 (see FIG. 2 (6)).
and the frame synchronization signal 1 (see 1('X) in FIG. 2(5)) output from the terminal '2'3 via the frame synchronization signal generation gate 5 are output with normal phases.

In addition, the first counter 6A above Natsu 1
The time axis 1 can also return to the normal state as soon as the synchronization pulse a is cleared by the next synchronization pattern. In addition, in the above operation,
Jitter supplementary F history earthenware? All used, sync pulse a and 1
The signal to be compared is made into a short pulse signal and has the required width.
If No. 8 contains a Ginocou component and the period of the same jO1 Hals a fluctuates, even if the second color/ri10
The time axis of is reassigned using the above synchronization pulse a as a reference, and the same 1υ] is followed within the synchronization. In addition, when a short pulse signal is used instead of the above window C, synchronization tracking (better, synchronization pulse d
As can be understood from Figure 4, there will be a delay of 1υ per round. Furthermore, if the synchronization pattern disappears due to a dropout or the like, the first counter 3A and the feedback pulses of the counters 10 and 7 of #5J2 will cause the self-pronounced "one o cycle" to be repeated. In the same case, the output signal from the JtlJ pattern separation gate 6 and the phase of the frame synchronization signal from the i3 generation gate 5 (as long as the jitter component is not a This means that they are synchronized, and if there is no drop completed in the fi number other than the same amount pattern, the division can be done normally)
Ru.

As described hereinafter, according to the present invention, when synchronization is achieved with multiple synchronization pulses, the synchronization pulse disappears due to a drop error, etc. even in this case. A drop alarm protection function in which a synchronization signal is output for each frame @: 11ifi occurs, and a pattern identical to the synchronization pattern contained in a digital signal other than the synchronization pattern occurs - but this is ignored. Thus, it is possible to provide a digital signal synchronization separation circuit that can prevent false synchronization.

[Brief explanation of the drawing]

Figure 1 (Circuit configuration diagram showing a conventional synchronous separation circuit, Figure 7)
The figure is a timing chart for explaining the operation of a conventional circuit, FIG. 6 is a circuit configuration diagram showing a synchronization separation circuit according to the present invention, and FIGS. 1 timing chart to do 1. There is again. 1 serial-parallel divider, n° synchronous pattern detection gate, 6A: first counter, 10: second counter, 4. synchronization pattern (u+ft) latch, 5 frame synchronization signal generation gate, 6: same 1v+ pattern separation gate, 7: first dropout sampling gate, 8: second dropout protection gate, 9: sickle correction Window generator, 11.0■ (Gate. Patent applicant: Akai City Machine Co., Ltd. Patent attorney: Minoru Kawagoe (Gate)

Claims (1)

[Claims] In a synchronization separation circuit that separates a synchronization pattern with a substantially constant period included in a digital signal when the digital signal is being transmitted, the synchronization separation circuit includes a synchronization pattern detector that detects a synchronization pattern with a constant period from the serial digital signal; and a second counter, a jitter correction window generator that generates a window in one frame according to the output of the first counter, and a frame synchronization signal generation gate that generates a complete synchronization signal in one frame io according to the output of the second counter. , a synchronization pattern separation latch that outputs the full timing at which the upper 8L synchronization patterns are all separated from the serial digital signal, and a synchronization pattern separation latch that outputs the entire upper 8L synchronization pattern from the serial digital signal, and
The sinter correction window generator is provided with a synchronous Bakun separation gate for separating the periodic pattern from the digital signal, and the sinter correction window generator is controlled by the time 1kl+ of the first counter, which is determined by the output of the same pattern detector. The return signal for each frame is returned to the input of the first counter, and the phase of the window and the output of the synchronization pattern detector are determined by 1. The time axis of the second counter is fully controlled 1 [~, the feedback signal for each frame based on the time axis is returned to the input of the second counter, and the frame synchronization signal generation gate and the synchronization pattern separation rasona are Output phase -r
1. A digital signal synchronization separation circuit characterized by: