JPS5980936A - Electronic parts - Google Patents
Electronic partsInfo
- Publication number
- JPS5980936A JPS5980936A JP15780283A JP15780283A JPS5980936A JP S5980936 A JPS5980936 A JP S5980936A JP 15780283 A JP15780283 A JP 15780283A JP 15780283 A JP15780283 A JP 15780283A JP S5980936 A JPS5980936 A JP S5980936A
- Authority
- JP
- Japan
- Prior art keywords
- film
- aluminum
- psg
- containing phosphorus
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Abstract
Description
【発明の詳細な説明】
本発明は、リンを含有する１）ンシリケートガラス（Ｐ
ＳＧ）膜やリンガラス（Ｐ、、０．４−８ ｉＯ，）膜
をパ・ソシベーション膜とする電子部品に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention provides 1) phosphorus-containing silicate glass (P
The present invention relates to electronic components using a phosphorus glass (P, 0.4-8 iO,) film as a passivation film.
ディスクリート半導体素子、バ・イボーラ形またはＭＩ
Ｓ形ＩＣ等のＰＮ接合を有する半導体装置においては、
表面安定化のため、Ｌ％Ｉ’ｆ’が大とでき種々のコン
タミネーションなゲッタリングひきるＰＳＧ膜をパッシ
ベーション膜とし°Ｃ使用するのが一般的である。Discrete semiconductor device, Bibora type or MI
In a semiconductor device having a PN junction such as an S-type IC,
In order to stabilize the surface, it is common to use a PSG film as a passivation film, which has a large L%I'f' and can avoid gettering of various types of contamination.
しかしながら−Ｐ Ｓ Ｇｌかり、耐湿性に劣り水分を
透過するため、ブルミニウム電１φｉ（配置ｒｑ）を腐
蝕させる欠点がある。この現象は、特に高濃度のリンを
含有するＰＳＧ膜やリンガラス膜において著じるしく、
デバイスの信頼性の低下をきたしている。しかしながら
、素子特性を変化させ１゛、かつ配線材料であるアルミ
ニウムを断六がさせないような平坦なＣＶＤＰＳＧ膜や
リンガラス膜を得るためには比較的低温でグラスフロー
アニールを行なう必要があり、そのためには高濃度のリ
ンを含有させる必要があり、多層配線技術としては重要
なことである。However, since -P S Gl is inferior in moisture resistance and permeates moisture, it has the disadvantage of corroding the luminium electrode 1φi (arrangement rq). This phenomenon is particularly noticeable in PSG films and phosphorus glass films containing high concentrations of phosphorus.
Device reliability is reduced. However, in order to obtain a flat CVDPSG film or phosphor glass film that changes the device characteristics and does not break the aluminum wiring material, it is necessary to perform glass flow annealing at a relatively low temperature. It is necessary to contain a high concentration of phosphorus, which is important for multilayer wiring technology.
そのため、従来、低温生成のできる耐湿性絶縁膜である
プラズマナイトライドＩＦＦをもって、リンを含有する
」二記したようプよパッシベーション膜を保護すること
が行なわれ−（いる。しかし、この１ｌｊＯものは、チ
ップ周辺等におい′〔、リンを含有するパッシベーショ
ン膜における１１１１壁が露出″５−る構造であるため
、Ｐ、０．の吸湿性によりそこからプラズマナイトライ
ド膜がはがされ、除々にそれが進行Ｌ７てリンを含んだ
水分が°ｒルミニウム電極（配め）にまで到達してそれ
を腐蝕させる欠点がある。Therefore, conventionally, a plasma nitride IFF, which is a moisture-resistant insulating film that can be generated at a low temperature, has been used to protect the passivation film containing phosphorus. Since the 1111 wall of the phosphorus-containing passivation film is exposed in the vicinity of the chip, etc., the plasma nitride film is peeled off from it due to the hygroscopicity of P,0. As the process progresses, the moisture containing phosphorus reaches the aluminum electrode (arrangement) and corrodes it.
それゆえ、本発明の目的Ｏ，耐湿件の悪い１１ンを含有
するバッジベージ日ン脱全面を耐湿性膜で被覆（７て電
極（配線）腐蝕等を防止し、もって高信頼度の半導体装
置等の電子部品を提供することにある。Therefore, the purpose of the present invention is to coat the entire surface of the badge-base film containing 11, which has poor moisture resistance, with a moisture-resistant film (7) to prevent electrode (wiring) corrosion, etc., and thereby improve the reliability of semiconductor devices, etc. Our goal is to provide electronic components.
以下、本発明の実施例である半導体装置を図面を参照し
ながら詳述−する、。Hereinafter, a semiconductor device which is an embodiment of the present invention will be described in detail with reference to the drawings.
図は、本発明にかかるＭＯ８ＩＣを示す縦断面図である
、同図において、１はＮ型シリコン基体、２はＰ＋型ド
レイン層、３はＰ″ツＬリソース層４はスクライブ領域
におけるＰ＋型層、５はフ２ｆ −ルド酸化シリコン膜
、６はゲート酸化シリコンＩＩＰ（。The figure is a longitudinal cross-sectional view showing a MO8IC according to the present invention. In the figure, 1 is an N-type silicon substrate, 2 is a P+ type drain layer, 3 is a P'' L resource layer 4 is a P+ type layer in the scribe region. , 5 is a field 2f-field silicon oxide film, and 6 is a gate oxide silicon IIP (.
７はゲート電極用多結晶シリコン膜、８はＰＳＧ膜、９
〜ｌＯはアルミニウム配線１．９ａはアルミニウムパッ
ド電極、１１はプラズマナイトライド膜である。7 is a polycrystalline silicon film for gate electrode, 8 is a PSG film, 9
~lO is an aluminum wiring 1.9a is an aluminum pad electrode, and 11 is a plasma nitride film.
本発明においては、耐湿性絶縁膜でかつ低温生成できる
、プラズマナイトライド膜１１をアルミニウムハツト１
１１．極９ａを除＜Ｉｃチップのほぼ全面に設けており
、バ、、、 ５／ベーシヨン眉である１）ＳＧＪＩＱ８
を完全に被覆す２・、ｌ、うＶｔ、設“（１ら旧ている
。In the present invention, a plasma nitride film 11, which is a moisture-resistant insulating film and can be generated at low temperature, is formed in an aluminum hat 1.
11. It is provided on almost the entire surface of the Ic chip except for pole 9a, and is 5/basion eyebrow 1) SGJIQ8
Completely covers 2., 1, Vt, and 1 (older than 1).
そのため、外部から侵入−「る水分かす〉′を含有Ｊ−
るＰＳＧ膜８に到達するのをプラズマナーｆ）ライド膜
１１によって防止しているため、配線金属であるアルミ
ニウム配ＦＪ９〜ｌＯの１〜蝕を防止し、デバイスの高
信頼性を得ることができる。／ｌ’♀に、グラスフロー
を行なうため高濃［ＩＵのリンを含有するｐｓａｐｌＡ
ｓを使用し、ているものにおいてル１．ＩＣチップ周辺
を完全に−ｒルミニ”） 、１＞ １口１２によって被
覆しており、１’ Ｓ Ｇ脆８直面を・全く外気にさら
していないため、ＰＳＧ膜８にηまれるリンが外部から
侵入する水分にとけ込み、リン酸とｌＩって配線や電極
をＩｐ、蝕させることはフ、（、い。Therefore, it contains moisture particles that enter from the outside.
Since the plasma nerf-ride film 11 prevents the plasma from reaching the PSG film 8, corrosion of the aluminum wiring FJ9-IO, which is the wiring metal, can be prevented and high reliability of the device can be obtained. . /l'♀, high concentration [psaplA containing IU of phosphorus] was added for glass flow
1. The periphery of the IC chip is completely covered with the 1> 1 opening 12, and the 1'SG brittle 8 surface is not exposed to the outside air at all, so that the phosphorus absorbed into the PSG film 8 is not exposed to the outside air. It is impossible for the phosphoric acid and lI to dissolve in the moisture that enters from the source and corrode the wiring and electrodes.
また、周辺がアルミニウム１模で被色されているため、
周辺のｐｓａ４ｑの耐湿のため、ＩＰ：ｉ別の工程を付
加しなくてもよい。In addition, because the surrounding area is colored with aluminum 1 pattern,
Because of the moisture resistance of the surrounding PSA4Q, there is no need to add a separate process for IP:i.
同様に、Ａ、ｅ膜を接地月１配糾止た目−基板コンタク
ト用の雷、極として用いることイ、できる。Similarly, the A and E films can be used as poles for grounding and substrate contacts.
図に示すものは、ＩＣチップ周辺の耐湿性膜どしてアル
ミニウム膜１２を使用し、他の領域をプラズマナイトラ
イド膜１１とした例である。このアルミニウムＪＪ！４
１２は電極お」、び配線５）〜１ｏの形成時に設けるこ
とができ、アルミニウムは水を通さないため、ＰＳＧ膜
８を保詐することができる。なお、アルミニウムの他に
多結晶シリコン脱等を使用することもできる。The figure shows an example in which an aluminum film 12 is used as a moisture-resistant film around an IC chip, and a plasma nitride film 11 is used in other areas. This aluminum JJ! 4
12 can be provided when forming the electrodes and wirings 5) to 1o, and since aluminum does not allow water to pass through, the PSG film 8 can be protected. Note that, in addition to aluminum, polycrystalline silicon removal etc. can also be used.
アルミニウム膜の下地として５モル％以下＜７）ＩＪン
（Ｐ、Ｏ，）を含有するＰ Ｓ Ｇ膜を設けておくこと
もできる。A PSG film containing 5 mol % or less of IJ (P, O,) can also be provided as a base for the aluminum film.
５モル％以下のリン（Ｐ、０． ）を含有１−るＰＳＧ
膜は、耐湿性が比較的良好で、菌濃度のリンを含有する
ＰＳＧ膜８から離間した領域に露出している表面を有し
ていても、横方向の水分の侵入が小さく、縦方向の水分
の侵入はプラズマナイトラ・イド膜１１によって防止で
きるため、このよ５１Ｊｒｍ造とすることができる。1-PSG containing 5 mol% or less of phosphorus (P, 0.)
The membrane has relatively good moisture resistance, and even though it has exposed surfaces in areas spaced apart from the PSG membrane 8 containing bacterial concentrations of phosphorus, it has little moisture intrusion in the lateral direction and low moisture penetration in the vertical direction. Since the intrusion of moisture can be prevented by the plasma nitride film 11, this 51Jrm structure can be adopted.
本発明は、ＭＯ８ＩＣに限定され１”、ダイオード、ト
ランジスタ、ＳＣＲ等のディスクリート半導体素子やバ
イポーラ形またはＭｌＳ形それに・・イブリッド形Ｉ
Ｃ管種々σ呼、Ｅ１様の電子部品に適用することができ
る。The present invention is limited to MO8IC, and is applicable to discrete semiconductor devices such as diodes, transistors, SCRs, bipolar type, MIS type, and hybrid type I.
C-tube can be applied to various types of σ and E1 type electronic components.
第１図は、本発明にかかるＭＯ３ＩＣの′＄、施例を示
１−縦断面１ン１である。
ｌ・・・Ｎ型シリコン基体、２〜・４・・・Ｐ＋型層、
５・・・フィールド酸化シリコン膜、６・・・ゲート酸
化シリコン膜、７・・・ゲート電極、８・・・ＰＳＧ膜
、９〜１０・・・アルミニウム配線、１１・・・プラズ
マナイトライド膜、１２−・−”Ｊ’ルミニウム（１す
。
代理人 弁理士 高 橋 ｊｌｌｌ 夫／：、”−
１１・）
１゜FIG. 1 is a longitudinal section 1-1 showing an example of MO3IC according to the present invention. l...N type silicon substrate, 2~.4...P+ type layer,
5... Field silicon oxide film, 6... Gate silicon oxide film, 7... Gate electrode, 8... PSG film, 9-10... Aluminum wiring, 11... Plasma nitride film, 12-・-"J' Luminium (1. Agent Patent Attorney Takahashi Jll Husband/:,"-
11・) 1゜
Claims (1)
ン膜の露出する部分はメタルまたはメタリックな部材に
て被覆されてなり、その他の上記パッシベーション膜の
露出部は、メタル部拐、メタリック部材及び耐湿性絶縁
部１１のうち少なくとも１つにより被覆されてなる電子
部品。1. The exposed part of the passivation film containing phosphorus around the chip is covered with metal or a metallic member, and the other exposed parts of the passivation film are covered with a metal part, a metallic member, and a moisture-resistant insulating part 11. An electronic component coated with at least one of the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15780283A JPS5980936A (en) | 1983-08-31 | 1983-08-31 | Electronic parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15780283A JPS5980936A (en) | 1983-08-31 | 1983-08-31 | Electronic parts |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12279076A Division JPS5348474A (en) | 1976-10-15 | 1976-10-15 | Electronic parts |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5980936A true JPS5980936A (en) | 1984-05-10 |
Family
ID=15657604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15780283A Pending JPS5980936A (en) | 1983-08-31 | 1983-08-31 | Electronic parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5980936A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61137347A (en) * | 1984-12-07 | 1986-06-25 | ゼネラル・エレクトリック・カンパニイ | Semiconductor chip |
| JPS63128733A (en) * | 1986-11-19 | 1988-06-01 | Sony Corp | Semiconductor device |
-
1983
- 1983-08-31 JP JP15780283A patent/JPS5980936A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61137347A (en) * | 1984-12-07 | 1986-06-25 | ゼネラル・エレクトリック・カンパニイ | Semiconductor chip |
| JPS63128733A (en) * | 1986-11-19 | 1988-06-01 | Sony Corp | Semiconductor device |
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