JPS5978754U - stereo demodulation circuit - Google Patents
stereo demodulation circuitInfo
- Publication number
- JPS5978754U JPS5978754U JP17357882U JP17357882U JPS5978754U JP S5978754 U JPS5978754 U JP S5978754U JP 17357882 U JP17357882 U JP 17357882U JP 17357882 U JP17357882 U JP 17357882U JP S5978754 U JPS5978754 U JP S5978754U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- signal data
- output signal
- data
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のスイッチング方式のステレオ復調回路の
ブロック図。第２図は本考案の一実施例を示すブロック
図。
１６．２５および２６・・・デジタル掛算器、１７゜２
７および２８・・・デジタルフィルタ、１８・・・演算
回路、１９・・・余弦波演算回路、２０・・・デジタル
信号処理形ＰＬＬ、２１〜２３・・・正弦波演算回路、
２４・・・デジタル加算器。FIG. 1 is a block diagram of a conventional switching type stereo demodulation circuit. FIG. 2 is a block diagram showing an embodiment of the present invention. 16.25 and 26...digital multiplier, 17°2
7 and 28...Digital filter, 18...Arithmetic circuit, 19...Cosine wave arithmetic circuit, 20...Digital signal processing type PLL, 21-23...Sine wave arithmetic circuit,
24...Digital adder.
Claims (1)
供給されて位相差検出出力データＤを出力するデジタル
信号処理形ＰＬＬと、該ＰＬＬからの位相差検出出力デ
ータＤが供給されてコンポジット信号中のパイロット信
号レベルをＰ１サブキャリヤの角周波数に等しい角周波
数をω。、コンポジット信号をサンプリングするサンプ
ルパルス毎に＋１される正の整数をｎ１サンプリングレ
ートをＴとしたとき、それぞれ−Ｐｓｉｎ（”ｎＴ＋Ｄ
）、−十２ ２ ｓｉｎ（ωｏｎＴ＋ ２Ｄ）および−Ｈ−５ｉｎ（ωｏ
ｎＴ＋ ２Ｄ）の演算をする第１、第２および第３の演
算回路と、前記入力信号データＡと前記第１の演算回路
の出力信号データとを加算するデジタル加算器と、該デ
ジタル加算器の出力信号データと前記第２の演算回路の
出力信号データと掛算をする第１のデジタル掛算器と、
前記デジタル加算器の出力信号データー′と前記第３９
演算回路の出力信号データとを掛算 〜する第２のデ
ジタル掛算器と、前記第１および第２のデジタル掛算器
の出力信号データをそれぞれ入力とする第１および第２
のデジ多ルロ′−パスフィルタとを備えてなることを特
徴とｊるステレオ−復調回路。[Claims for Utility Model Registration] A digital signal processing type PLL that is supplied with input signal data A obtained by A/D converting a composite signal and outputs phase difference detection output data D, and a phase difference detection output data D from the PLL. The pilot signal level in the composite signal is supplied with an angular frequency ω equal to the angular frequency of the P1 subcarrier. , -Psin("nT+D
), -12 2 sin (ωonT+ 2D) and -H-5in (ωo
nT+2D); a digital adder that adds the input signal data A and the output signal data of the first calculation circuit; a first digital multiplier that multiplies the output signal data and the output signal data of the second arithmetic circuit;
The output signal data' of the digital adder and the 39th
a second digital multiplier that multiplies the output signal data of the arithmetic circuit; and first and second digital multipliers that receive the output signal data of the first and second digital multipliers, respectively.
A stereo demodulation circuit comprising a digital multi-pass filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17357882U JPS5978754U (en) | 1982-11-18 | 1982-11-18 | stereo demodulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17357882U JPS5978754U (en) | 1982-11-18 | 1982-11-18 | stereo demodulation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5978754U true JPS5978754U (en) | 1984-05-28 |
| JPS6238362Y2 JPS6238362Y2 (en) | 1987-09-30 |
Family
ID=30378097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17357882U Granted JPS5978754U (en) | 1982-11-18 | 1982-11-18 | stereo demodulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5978754U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62225039A (en) * | 1986-03-27 | 1987-10-03 | Matsushita Electric Ind Co Ltd | Multiplex demodulator |
-
1982
- 1982-11-18 JP JP17357882U patent/JPS5978754U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62225039A (en) * | 1986-03-27 | 1987-10-03 | Matsushita Electric Ind Co Ltd | Multiplex demodulator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6238362Y2 (en) | 1987-09-30 |
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