JPS58134547A - Stereophonic pilot signal eliminating circuit - Google Patents

Abstract

PURPOSE:To remove a stereophonic pilot signal completely by imposing pulse- width modulation on a pulse position modulated signal by a cancel signal for the stereophonic pilot signal removal and removing the stereophonic pilot signal, and using this pulse-width modulated signal as an FM detection signal. CONSTITUTION:The circuit consisting of an OR circuit 53, capacitor 54 and resistance 55, and level comparator 57 operates as a monostable multivibrator and is triggered by a rise of an FM signal A, obtaining a pulse string signal with specific width determined by the capacitor 54 and resistance 55 as far as a reference level is a constant bias voltage. This pulse train signal is a PPM signal and its low frequency component is a composite signal containing a pilot signal of 19kHz. As the reference signal of a level comparator 57, an out-of-phase pilot signal is superposed on a specific bias, so a PWM signal varying in pulse width according to the cancel signal appears at the output of the comparator 57.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stereo/4' pilot signal removal circuit,
In particular, the present invention relates to a circuit for removing stereo/quadrature signals in an FM detection circuit.

In an FM stereo chainer, there is a so-called MPX (multiplex) demodulator for independently separating left and right channel signals from a stereo composite signal that is a PM signal. A subcarrier signal of 38kHz is generated by obtaining a signal of 19&Hg from the subcarrier signal, and demodulation is performed by using this subcarrier signal as a switching signal.

Since this composite signal includes the stereo/matrix signal, the subcarrier signal switching separation circuit also switches the stereo/matrix signal and mixes it into the left and right channel signals. As a result, this causes a decrease in the S value of the demodulated stereo signal, so attempts have been made to remove this signal using a Toranozo circuit or a filter circuit. It will cause deterioration.

Therefore, a circuit system has been proposed in which the stereo pilot signal is canceled at the input stage of the MPX demodulator. In particular, a PLL (phase-locked drousot) circuit is used to selectively extract a somewhat complex signal from a composite signal and obtain a subcarrier signal synchronized with this signal. (J&
There is a method in which a Hg rectangular wave signal is used as a main lot cancellation signal, and the lump cancellation signal is added to a composite signal at the input stage of a switching separation circuit.

Kaka・　′□′1:.

In this method, the circuit configuration is simple, but since the cancellation signal is a rectangular wave, a new 19kHz signal component is generated by its harmonic components and the 38Hz subcarrier switching signal, which makes the switching separation circuit difficult. Even if the Gyrot signal is completely canceled at the input stage, 19&Hg unnecessary waves appear at the output stage, which is not desirable.

Therefore, it is an object of the present invention to provide a stereo signal that can very easily and completely remove the stereo/main signal.
An object of the present invention is to provide a motherboard signal removal circuit.

The stereo/matrix signal removal circuit according to the present invention is a stereo/matrix signal removal circuit in an FM detection circuit which detects an FM signal by obtaining a pulse position modulation signal having a stereo composite signal frequency component from an FM signal. Its features are: - Te-Cruz width modulation of the Cruz position modulation signal into a cancellation signal for removing the stereo pilot signal * - □: Teleo-
1, ′ by removing the ilot signal.

This pulse width modulation signal is used as an FM detection signal. That's what I did.

The present invention will be explained below using the drawings.

FIG. 1 is a block diagram illustrating the present invention in detail;
The M-IP (intermediate frequency) signal is detected by an F'M detector 1 and applied to a PLL circuit 2. In this PLL circuit 2, a 38&Hg sine wave subcarrier signal (*ωst) synchronized with the 19&Hg stereo/zoot signal in the FM detection output and a 19&Hg sine wave/mother block cancellation signal are generated. The configuration will be described later using FIG. 4.

F'M-IF with carrier frequency of 10.7MHz
The double signal is beat down by the frequency converter 3 and the LPF 4 and converted into an FM signal having a carrier frequency of, for example, 1.26 MHz. A detector that converts this FM signal into a stereo composite signal and detects it.
A pulse train signal generator 5 is provided, and the low frequency component of the output of the pulse train signal generator 5, that is, the stereo composite signal component is transmitted to the next stage multipliers 6 to 9 and an adder 10.
, 12 is introduced into a switching type MPX demodulator. In this i4 pulse train signal generator 5, PLL
The 1 (lHg) pilot signal is removed using the pilot cancellation signal obtained from the circuit 2.More specifically, this main pulse train signal generator 5
is basically a monostable multivibrator that is triggered by the rising edge of the FM signal that is the output of LPF' 4, so its output has a constant pulse width of PPM (A' pulse position modulation). A signal is obtained, the low frequency component of which contains the frequency components of the stereo composite signal. This PPMFM signal is subjected to PWM (-e pulse width modulation) by the cancellation signal of the LL circuit, and this cancellation signal has a frequency of 194Hz.
A signal is used that has the opposite phase and the same level as the stereo signal, which is a sine wave.

In other words, the PPMFM signal containing the stereo composite signal (/f (including the Ot signal) component) is a 19 kHz sine wave that is in opposite phase and at the same level as the mother pilot signal.
By performing the WM processing, the low-frequency components of the PWM signal become only the main and sub signal components that do not contain the pilot signal, making it possible to cancel the pilot signal.

pM detection output e(t) which is the PWM wave obtained in this way
becomes one input of multipliers 6 and 8, and the negative phase signal e (t) from inverter 3 becomes one input of multipliers 7 and 9, and these signals g (t) and e (t)
Used as a switching signal for demodulation.

The 38&)ig sine wave carrier signal image ω8t from the PLL circuit 2 is the other input to the multipliers 7 and 8, and the negative phase signal ω8t from the inverter 2 is the other input to the multipliers 6 and 9.
It becomes another input and is used as a signal to be switched.

The outputs of the multipliers 6 and 7 and the PWM signal e (t) are added in an adder circuit IO, and the result is outputted from the right channel via the LPF 14. Further, the outputs of the multipliers 8 and 9 and the PWM signal e (t) are added in the adder circuit 11, and the LPF 1
5 to become the left channel output.

1. FIG. 2 is a circuit diagram showing an embodiment of the pulse train signal generator 511 in FIG. 52 and becomes the input of the orto 53, that is, the trigger input (B). This or? -G53
The output of the dart 53 is applied to one input of the level comparator 57 through a time constant circuit including a capacitor 54 and a resistor 55, so that the output of the dart 53 and the input of the comparator 57 are AC-coupled. The output of the comparator 57 and the other input of the f-to-53 are directly connected, that is, DC-coupled, and the output (E) of the comparator 57 is used as the detection output. This comparator 5
As the comparison level (C) of 7, is there a reference bias?
A pilot cancellation signal is used in a superimposed manner. A resistor 58 is used to apply a bias, and a resistor 59 and a capacitor 60 are used to apply a pilot cancel signal. Further, the diode 56 and the capacitor 54 are instantaneously discharged to reset the capacitor 54.

FIG. 3 is a waveform diagram of each part of the circuit in FIG. 2, and (A),
(B), (C) and (FM input IN, respectively)
Trigger input, level comparison signal 4'j, -4 to serial output OU
(D) is a waveform showing the signal from the comparator 5702. If the level comparator 570 reference level is a constant bias voltage, this circuit operates as a normal monostable multivibrator, and is triggered by the FM signal upstream and receives a pulse train of constant width determined by the capacitor 54 and resistor 55. is obtained. This signal train signal is a PPMFM signal, and its low frequency component is 19 kHz2zJ
? This is a stereo condigit signal including a pilot signal. Since the level comparator 570 reference signal is superimposed with a 19&Hz negative phase/mother signal (cancellation signal) on a constant bias, the output of the comparator 57 is a PWM whose pulse width changes according to this cancellation signal. I get a signal. Therefore, by adjusting the level of this cancellation signal using the variable resistor 59, the pilot signal is canceled out and no longer exists in the PWM signal.

The low frequency component e(t) of the PWM signal with is e(#)=V
, +αIM(t)+5(t)shaωst) −・
−(1), main signal M(t), sub signal S
(t) stnω8 and DC component V. Only. α
is a constant. Therefore, the output α(1) of the multiplier 6 is α(1)=−ω8t・(v, ten α(M(t)+8
(t) ω8t)]・・・・・・・・・ (2) It becomes. Also, the output i (#) of the inverter 13 is e
(t)=CI −V, )−cl M(t)+S (t
) sin ωst 1 ... river (3), so the output b(t) of the multiplier 7 is b(t)=dmωst ・
((1-V, ) -cl (M(t)+5(t) self ω
8t)] ・Four songs (4). Therefore, the output of the adder 10 is α(t) + b (t)Ag (t) = V, +
αM(#) + (1-2V, )dnω8 to 1α8Ct)
*ω8t-2αM(t)tIkω8t-2α8(t)m
2ωs t −song (s). Here, −2(X 5(t)tn” w st =−cX 5(
t) 10 αS (j) am2 ωst... (6) If Vo=J4+, then a (12Vo)
5iinωs t=0, the steady 38&Hz subcarrier component is canceled out, and unnecessary frequency components are further canceled out, which is advantageous. The output of LPF14 has R,'(t) = v, +6M(t)-α5
(t)=Vo+2αR(t)・・・・・・・・・・・・
(7) Therefore, only the right channel signal R(t) is output. Similarly, only the left channel signal is derived from the output of the LPF 15.

FIG. 4 shows a specific example of the PLL circuit 2, in which the phase of the pilot signal is compared with the output of the frequency divider 22 in the phase comparator 21, and the output is sent to the VCO (voltage controlled oscillator) via the LPF 23 and the DC angle 24. )250 control input.

The VCO 25 generates a 76 kHz i9 pulse train signal, and the 138 kHz signal, which is the output of the 1' frequency divider 26, is converted into a sine wave by the LPF 27, and this is used as a subcarrier signal. This LPF output is again made a little bit smooth by the limiter 28, and this pulse train signal is further made into 19&Hg by the frequency divider 22 to be used as a single power source for the comparator 21, and the LPF 29 makes it a sine wave having the same phase as the pilot signal. A signal is obtained, which is reversed in phase by the inverter 31 and converted to a signal of 19kHz/'.
A P-lot cancellation signal can be obtained.

As described above, according to the present invention, it is possible to cancel the four-plot signal in the FM detection stage with an extremely simple configuration, and to cancel the mother-lot signal using the signal train signal containing the composite signal component. M because it is a thing
There is an advantage that unnecessary beats are not generated during PX stereo demodulation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an FM stereo tuner using an embodiment of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, FIG. 3 is a waveform diagram showing the operation of the circuit in FIG. Figure 4 is m1
1 is a 1° circuit diagram showing a specific example of the PLL circuit shown in the figure. Explanation of symbols of main parts 2... PLL circuit 5... Bus pulse train signal generator, 53... Or dirt 54... Capacitor 5
7. Level comparator applicant: Guionia Co., Ltd. agent Motohiko Fujimura, patent attorney

Claims (3)

[Claims] (1) By obtaining the self-position modulation signal from the FM signal, which has the frequency components of the stereo composite signal
This is a stereo/matrix signal removal circuit in the FM detection circuit that detects the M signal. With the cancellation signal of the stereo signal, the position modulation signal is
A stereo pilot signal removal circuit characterized in that the stereo/four pilot signal is removed by self-width modulation, and the pulse width modulated signal is used as an FM detection signal. (2) The circuit according to claim 1, wherein the self-position modulation signal is obtained from a monostable multivibrator that receives the FM signal as input. (3) The monostable multivibrator has an ff-) circuit which receives a trigger signal based on the FM signal as one input, and an input that is AC-coupled with the output of the r-) circuit, and has an input that is AC-coupled with the output of the r-) circuit, and is connected to the extraction input of the dart circuit. and a level comparator circuit having a DC-coupled output, the comparison signal of the level comparator circuit being ac! 3. The circuit according to claim 2, wherein the circuit is adapted to be changed in accordance with the cancellation signal.