JPS636179B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stereo demodulator, and more particularly to an FM stereo multiplex demodulator that separates left and right channel signals by multiplying a rectangular wave subcarrier signal and a stereo composite signal.

There is a circuit system that separates left and right channel signals by switching a stereo composite signal, which is the FM detection power, using a rectangular wave subcarrier signal. Figure 1 is a block diagram of such a demodulation system, and the FM-IF (intermediate frequency) signal is transmitted to the FM detector 1.
The signal is converted into a composite signal and applied to a switching circuit 3 via an LPF (low pass filter) 2 that removes unnecessary components. PLL the 19kHz pilot signal contained in the output of LPF2.
A 38 kHz rectangular wave subcarrier signal extracted in the (phase-locked loop) circuit 4 and phase-synchronized with this pilot signal is used as a switching signal in the switching circuit 3 described above. The left and right channel signals, which are audio components, are separated and derived from this switching output.
For this purpose, LPFs 5 and 6 are provided.

Here, since the 38kHz subcarrier signal which is the switching signal is a rectangular wave as shown in Figure 2A, if this is expanded into a Fourier series, F(t)=4/πsinω _S t+4/3πsin3ω _S t+4
/5πsin5ω _S t+...(1) Here, ω _S is the angular frequency of the subcarrier signal. In this way, the frequency spectrum of F(t) includes odd harmonics such as 114kHz, 190kHz, . . . in addition to the fundamental wave of 38kHz, as shown in FIG. 2B.

If the FM detection output is switched using the switching signal F(t) having such a frequency spectrum, both signals will be multiplied.
Hz, the detector output appearing in the stereo output by this multiplication becomes as shown in FIG. 2C. In other words, main signal (0~15kHz) and sub signal (38±15kHz)
In addition, signals at 114±15kHz, 190±15kHz, etc. (miscellaneous, nearby interference waves, etc.) are also demodulated and output.

In order to prevent this drawback, the output of the FM detector 1 is set to 114kHz, 190kHz,... as shown in Figure 2D.
...It becomes necessary to add an LPF with a large amount of attenuation in the vicinity. However, since 114kHz is close to the composite signal component, this LPF
As shown in FIG. E, the delay characteristics of the composite signal are no longer flat, the amplitude characteristics are no longer flat, and the distortion and separation characteristics of the stereo demodulated output are deteriorated.

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a stereo demodulation device with good characteristics.

The stereo apparatus according to the present invention generates a demodulated channel by adding the channel signal obtained by multiplying the stereo composite signal by a multiplication signal synchronized with the stereo pilot signal separated from the stereo composite signal and the stereo composite signal. In the stereo demodulation circuit that obtains the signal,
The multiplication signal includes a first rectangular wave signal having the same phase and the same period T as the subcarrier signal of the stereo composite signal, and a first rectangular wave signal that is synchronized with the first rectangular wave signal, has twice the frequency of the subcarrier signal, and has the same period T as the subcarrier signal of the stereo composite signal. The second rectangular wave signal includes a frequency component having a phase difference of T/8 with respect to the first rectangular wave signal.

The present invention will be explained below using the drawings.

FIG. 3 is a block diagram showing the principle of the present invention, in which the stereo composite signal C(t), which is the FM detection output, is input to multiplier circuits 1 and 2, respectively, and one input to each of adder circuits 3 and 4. It's summery. In the multiplication circuits 1 and 2, the multiplication signals U ₁ (t) and U ₂ (t) as the first rectangular wave signals are multiplied by the previous stereo composite signal C(t), respectively. These multiplication outputs v ₁ (t) and v ₂ (t)
are input to each of adder circuits 3 and 4, and are input to multiplier circuits 5 and 6, respectively. In the multiplication circuits 5 and 6, the multiplication signal U ₃ (t) as a second rectangular wave signal is multiplied by the previous multiplication outputs v ₁ (t) and v ₂ (t), respectively, and these multiplication outputs v ₃ (t), v ₄
(t) serves as one input to each of adder circuits 3 and 4. The left and right channel signal outputs v _L (t) and u _R (t) are derived from the outputs of these adder circuits 3 and 4, respectively.

Each of the multiplication signals U ₁ (t) to _{U 3} (t) described above is
This signal is obtained by a PLL (phase locked loop) circuit 7, and is a rectangular wave signal synchronized with the 19kHz stereo pilot signal in the stereo composite signal _. t) to U ₃ (t) is shown.

The multiplication signals U ₁ (t) and U ₂ (t) are rectangular wave signals of 38 kHz subcarrier signals, and have positive and negative phases that are synchronized with a 19 kHz stereo pilot signal and have a fundamental wave twice the frequency of this pilot signal. It is a square wave. Moreover, the multiplication signal U ₃ (t) is calculated by applying the square wave signal period T to the square wave signals U ₁ (t) and U ₂ (t).
This is a rectangular wave signal having a fundamental wave shifted by 1/8 of the frequency of the stereo pilot signal and having a fundamental wave four times the frequency of the stereo pilot signal (76 kHz=2ω _S ).

Square wave signals U ₁ (t) to U ₃ (t) for these multiplications
is generated by the PLL circuit 7 shown in FIG.
That is, the 19kHz stereo pilot signal in the composite signal becomes one input of the phase comparator 71, and is compared in phase with the output of the 1/2 frequency divider 72.
This phase comparison output is passed through a low pass filter 73,
VCO (voltage controlled oscillator) via DC amplifier 74
75 control signals. This VCO75 is 304kHz
It generates a pulse train signal, and this output is sent to two D-FF (delayed flip-flop) 76,
77 serves as an input to a ring counter.
In other words, the output of VCO75 is used as the trigger input for D-FF76 and 77, and the output of D-FF77 is used as the trigger input for D-FF76 and D-FF77.
It becomes the data input of FF76, and the Q output of D-FF76 becomes the data input of D-FF77. Then, the Q output of the D-FF 76 is used as a trigger input of the D-FF 78, and the frequency is divided into 1/2. This D-FF
78 Q, output is multiplication signal U ₁ (t) and U ₂ (t)
The Q output of D-FF77 is the multiplication signal.
It becomes U ₃ (t). Note that the output of D-FF77 is output as signal U ₄ (t), and D-FF78
The output becomes the input to the 1/2 frequency divider 72 mentioned above.

Figure 6 shows the signal waveforms of each part of the PLL circuit 7 in Figure 5, and the VCO synchronized with the 19kHz pilot signal.
75 304kHz pulse train signals are generated.
The output of this VCO75 is divided into 1/4 by the ring counter of D-FF76 and 77 to 76kHz (19×
4kHz) square wave, each D-FF76,
77, the output is obtained as a signal as shown in the figure. D-Divide the Q output of FF76 into 1/2
FF78Q, the output is the signal U ₁ (t), U ₂ shown in the figure.
(t) is a positive and negative phase signal with a fundamental wave of 38kHz.

In such a configuration, the stereo composite signal C(t) is expressed as C(t)=L(t)+R(t)+{L(t)−R(
t) sinω _S t (2), each multiplication signal U ₁ (t) to _{U 3} (t) is expressed by the following equation. Note that L(t) and (t) indicate left and right channel signals, respectively.

U ₁ (t) = (4/π) sinω _S t + (4/3π) sin3
ω _S t+(4/5π) sin5ω _S t+……(3) U ₂ (t)=(4/π) sinω _S t−(4/3π) sin3
ω _S t−(4/5π) sin5ω _S t+……(4) U ₃ (t)=(4/π) sin2ω _S (t−T/8)+(4/3
π) sin6ω _S (t-T/8)+(4/5π) sin10ω _S (t
-T/
8) +... (5) Here, T=2π/ω _S , and ω _S is the angular frequency of the 38kHz subcarrier.

The outputs v ₁ (t) and v ₂ (t) of the multiplier circuits 1 and 2 are as follows: v ₁ (t)=C(t)・U ₁ (t) ……(6) v ₂ (t)=C(t )・U ₂ (t) ...(7), and the outputs of multiplier circuits 5 and 6 are v ₃ (t), v ₄ (t)
is the following formula.

v ₃ (t)=C(t)・U ₁ (t)・U ₃ (t)=C(t)・
(4/π) [(√2−1) sinω _S t −{(√2+1)/3} sin3ω _S t−{(√2+1)
/5}sin5ω _S t+{(√2-1)/7}sin7ω _S t+…
…]
……(8) v ₄ (t)=C(t)・U ₂ (t)・U ₃ (t)=C(t)・
(4/π) [(√2−1) sinω _S t −{(√2+1)/3} sin3ω _S t−{(√2+1)
/5}sin5ω _S t+{(√2-1)/7}sin7ω _S t+…
…]
...(9) Therefore, in adder circuits 3 and 4, C(t), v ₁
(t), v ₃ (t) and C(t), v ₂ (t), v ₄ (t) in the ratio of 4√2:π(√2+1):π, each addition output v ₁ (t) and v _R (t) are v _L (t)=4√2C(t)+π(√2+1)v ₁ (t)+
πv ₃ (t) =4√2C(t) {1+2sinω _S t+(2/7)
sin7ω _S t + (2/9) sin9ω _S t+...} ...(10) v _R (t)=4√2C(t)+π(√2+1)v ₂ (t)+
πv ₄ (t) =4√2C(t) {1−2sinω _S t−(2/7)
sin7ω _S t − (2/9) sin9ω _S t+...} ...(11) Considering only the audio components in v _L (t) and v _R (t), v _L (t)=8√2L(t)...(12) v _R (t)8√2R(t)... (13) Thus, the left and right channel signals are derived separately. Since the addition signals shown by equations (10) and (11) do not include the third and fifth harmonic components of the subcarrier signal, bead interference due to these harmonic components does not occur.

FIG. 7 is a circuit diagram showing a specific example of the circuit shown in FIG. 3, in which switching elements Sw ₁ and Sw ₃ constitute a multiplication circuit 1, and switching elements Sw ₂ and Sw ₄ constitute a multiplication circuit 2. It also has a switching element.
Sw ₅ and Sw ₇ form the multiplier circuit 5 and the switching element
Sw ₆ and Sw ₈ constitute a multiplication circuit 6, respectively.
Addition circuits 3 and 4 are configured by the operational amplifier OP ₁ and the resistor R ₇ , and by the operational amplifier OP ₂ and the resistor R ₈ , respectively. Switching elements Sw ₁ and Sw ₄ are switched by the multiplication signal U ₁ (t), and switching elements Sw ₂ and Sw ₃ are switched by the multiplication signal U ₂ (t).
Switching is performed by switching element
Sw ₅ and Sw ₈ are switched by the multiplication signal U ₃ (t), and switching elements Sw ₆ and Sw ₇ are switched by the opposite phase signal U ₄ (t) of the multiplication signal U ₃ (t).

In such a configuration, in order to achieve the best separation (separation degree of left and right channel signals) and optimal combination ratio, R ₁ = R ₂ , R ₃ = R ₄ , R ₅ = R ₆ 4√2R ₁ = π( √2+1)R ₃ =πR ₅ }
...(14) Each resistor R ₁ to _{R 6} should be selected so as to satisfy the following relationship.

FIG. 8 is a diagram showing another specific example of the circuit in FIG. ₃ , in which a balanced differential type switch circuit is used _as the multiplier circuit, and a composite signal C (t ) is applied and the resistance
The addition ratio is determined by R ₁ , R ₃ , R ₄ and R ₂ , R ₅ , R ₆ . Transistors Q ₁ to Q ₄ and Q ₅
~ _Q8 is a double balanced differential switch circuit, 38k
It is switched by Hz rectangular waves U ₁ (t) and U ₂ (t). The outputs of transistors Q ₁ to Q ₄ are connected to the left and right switching output terminals, and the outputs of transistors Q ₅ to Q 4 are connected to the left and right switching output terminals.
The output of Q ₈ is input to a double balanced differential switch circuit consisting of transistors Q ₉ to Q ₁₂ .
The 76kHz rectangular waves U ₃ (t) and U ₄ (t) are switched and combined at the left and right channel output ends.

In this circuit, R ₃ = R ₄ , 8R ₁ / {π(√2+1)−4} R ₅ /R ₃ = R ₆ /R ₄ = R ₂ /R ₁ =√2+1)}
...(15) is the condition for achieving the best separation and eliminating beat interference.

Note that the present invention is not limited to the principle diagram shown in FIG. 3, and various configurations are possible without departing from the spirit of the present invention.

For example, in FIG. 3, the multiplier circuits 5 and 6 output the composite signal C(t) and the multiplier signals U ₁ (t), U ₂
(t) and the multiplication signals U ₂ (t) and U ₃ (t) from _the PLL circuit.
U ₃ (t) and U ₂ (t) to _{U 3} (t) may be generated.

Also, v ₁ (t)=C(t)・v ₁ (t) in equation (6) and v ₃ (t)=C(t)・U ₁ (t)・U ₃ (t ) and (√2
+1): Considering the field added with the ratio of:, the added output v ₅ (t) is v ₅ (t) = C(t)・(4/π) {2√2 sinωst +2√2/7 sin7ωst … …} …(16) Then, by further expanding the above equation, v ₅ (t)=8√2/π[{L(t)−R(t)}+{L
(t) +R(t)}sinωst−{L(t)+R(t)}sin7
ωst
……] ……(17) becomes. As is clear from the above equation, the audio signal component is a stereo sub-signal, and does not include the third and fifth harmonic components of the subcarrier signal.

Therefore, the stereo sub-signal obtained from the addition signal v ₅ (t) shown in equation (17) and the main signal in the composite signal are passed through a matrix circuit so as to be added and subtracted at a ratio of 1:8√2/π. By doing so, left and right stereo signals can be obtained.

Furthermore, v ₂ = C(t)・U ₂ (t) in equation (7) and v ₄ in equation (9)
Of course, a similar sub-signal can be obtained by adding (t)=C(t)·U ₂ (t)·U ₃ (t) at a predetermined ratio as described above.

As described above, the present invention has the advantage of being able to eliminate beat interference caused by harmonics three times or five times the subcarrier signal frequency included in the switching signal (multiplying signal). Furthermore, by adopting the switching method, characteristics such as S/N, distortion, and separation can be optimized, making it suitable for use in an FM stereo multiplex demodulation circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional stereo demodulation device, Fig. 2 is a diagram explaining the characteristics of the device in Fig. 1,
FIG. 3 is a block diagram showing the principle of the present invention, FIG. 4 is an operation waveform diagram of the block in FIG. 3, FIG. 5 is a diagram showing a specific example of the PLL circuit of the block in FIG. 3, and FIG. The waveform diagram of each part of the circuit in FIG. 5, and FIGS. 7 and 8 are circuit diagrams showing specific examples of the blocks in FIG. 3, respectively. Explanation of the symbols of the main parts: 1, 2, 5, 6...multiplication circuit, 3, 4...addition circuit, 7...PLL circuit.

Claims (1)

[Claims] 1. A channel signal obtained by multiplying the stereo composite signal by a multiplication signal synchronized with a stereo pilot signal separated from the stereo composite signal and the stereo composite signal are added to form a demodulated channel. A stereo demodulation circuit for obtaining a signal, wherein the multiplied signal has the same phase and the same period T as the subcarrier signal of the stereo composite signal.
a first rectangular wave signal, and a frequency component that is synchronized with the first rectangular wave signal, has a frequency twice that of the subcarrier signal, and has a phase difference of T/8 with respect to the first rectangular wave signal. A stereo demodulator characterized in that it includes two rectangular wave signals.