JPS6238362Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a stereo demodulation circuit used in an FM tuner, and more specifically to a digital stereo demodulation circuit that obtains a stereo demodulation output from a composite signal through digital signal processing.

(Prior Art) A conventional analog type stereo demodulation circuit, in the case of a switching type, has a phase comparator 1, a loop filter 2, a DC amplifier 3, a voltage controlled oscillator 4, and a 1/2 The input terminal 1 is connected to the input terminal 1 by a PLL circuit 7 consisting of a frequency divider 5 and a 1/2 frequency divider 6.
A 19kHz pilot cancel signal whose phase is synchronized with the pilot signal (hereinafter referred to as the reference pilot signal) in the composite signal supplied to the
A 38 kHz switching pulse is obtained, the reference pilot signal is removed from the composite signal in the pilot cancel circuit 8, and the output signal of the pilot cancel circuit 8 and the 38 kHz switching signal of opposite phase output from the 1/2 frequency divider 5 are obtained. Similarly, the output signal of the pilot cancel circuit 8 and the positive-phase 38kHz switching signal output from the 1/2 frequency divider 5 are multiplied in the analog multiplier 10, and the The output signals of the amplifiers 9 and 10 were outputted through low-pass filters 11 and 12 for stereo demodulation.

However, when using the above-mentioned conventional switching type stereo demodulation circuit, it is necessary to adjust the voltage controlled oscillator, and there is a drawback that drift occurs due to temperature, humidity, aging, etc. Furthermore,
In order to demodulate interfering signals such as interference from adjacent stations, a baseband filter is required, which deteriorates the degree of separation, and the use of a pilot cancel circuit has the disadvantage of deteriorating the S/N ratio. Furthermore, in a switching type stereo demodulation circuit, the degree of separation is theoretically only 13 dB, and a filter with steep characteristics is required to remove the subcarrier (38 kHz) sideband, and variations in filter characteristics can cause distortion. There was a drawback that the characteristics, frequency characteristics, and S/N characteristics deteriorated.

On the other hand, there is also a stereo demodulation circuit using a sampling-and-hold method. In this case, since the sampling frequency was low, there was a drawback that the frequency characteristics deteriorated.

(Purpose of the invention) The present invention has been made in view of the above, and eliminates the above drawbacks, eliminates the need for adjustment of the voltage controlled oscillator, has infinite separation, has a flat frequency characteristic, and eliminates interference. The object of the present invention is to provide a stereo demodulation circuit that does not generate waves.

The present invention will be explained below with reference to examples.

(Configuration of one embodiment of the present invention) FIG. 1 is a block diagram showing an embodiment of the present invention.

20 is a digital signal processing type PLL consisting of a digital multiplier 16, a digital filter 17, an arithmetic circuit 18, and a cosine wave arithmetic circuit 19, in which the reference pilot signal and cosine in the input signal data A obtained by A/D conversion of a composite signal are Phase difference detection output data D corresponding to the phase difference with the output signal data E of the wave calculation circuit 19 is output.

The output of the digital signal processing type PLL 20 is supplied to sine wave calculation circuits 21 to 23. Sine wave calculation circuit 2
1 calculates Qsin(ω ₀ /2nT+D), the sine wave calculation circuit 22 calculates 1/2+sin(ω ₀ nT+2D), and the sine wave calculation circuit 23 calculates 1/2−sin(ω ₀ nT+2D). Let's do it. Here, ω ₀ is the free run angular frequency of the cosine wave calculation circuit 19, and is set equal to the angular frequency ω _s (=2π·38000) of the subcarrier.

The input signal A and the output data of the sine wave calculation circuit 21 are added by a digital adder 24, and the output data of the digital adder 24 and the output data of the sine wave calculation circuit 22 are multiplied by a digital multiplier 25, and then digital addition is performed. output data of the device 24 and the sine wave calculation circuit 23
The digital multiplier 26 multiplies the output data of . The output data of the digital multipliers 25 and 26 are respectively filtered through a digital low-pass filter 27.
and output via 28.

(Operation of an embodiment of the invention) In an embodiment of the invention constructed as described above, a composite signal is input to the input terminal 1N _-1 .
D-converted input signal data A is supplied.

Input signal data A is expressed by the following equation.

A=(L+R)+(L-R)sinω _S nT +Psinω _S /2nT Here, L is the left channel audio signal, and L=lsin
(ω _L nT + α _L ), R is the right channel audio signal, R = r sin (ω _R nT + α _R ), l,
r, ω _L , ω _R , α _L , and α _R indicate the amplitude, angular frequency, and phase of the left channel audio signal and right channel audio signal, respectively. Further, T is a sampling rate, and n is a positive integer, which is incremented by 1 every sampling clock. P is the pilot signal level.

The cosine wave calculation circuit 19 is a digital signal processing type
PLL phase difference detection output data, i.e. arithmetic circuit 1
8 using the argument ω ₀ /2nT+D, and outputs cosine wave data. Therefore, the output data E of the cosine wave calculation circuit 19 is expressed as E=cos(ω ₀ /2nT+D). Here, ω ₀ =ω _S is set.

Therefore, the output data B of the digital multiplier 16
B=A×E=[(L+R)+(L-R)sinω _S nT +Psinω _S /2nT]cos( _ω0 /2nT+D) =(L+R)cos( _ω0 /2nT+D) +(L-R)1 /2sin [(ω _S +ω ₀ /2)nT+D
] +(L-R)1/2 [(ω _S -ω ₀ /2nT)-D] +P1/2sin [(ω _S /2+ω ₀ /2)nT+D] +P1/2sin [(ω _S /2-ω ₀ /2)nT-D].

The output data C of the digital filter 17 is expressed as follows, assuming that the phase delay caused by the digital filter 17 is θ.
High frequency components are removed and C=P1/2sin [(ω _S /2-ω ₀ /2)nT-D+
θ].

Since ω _S =ω ₀ , the output signal data C has a very low frequency, and the phase delay θ is almost negligible and can be ignored. Therefore, the output data C becomes C=P1/2(-D)=-PD/2.

The arithmetic circuit 18 is an arithmetic circuit that adds (2KC) to the value of the old output signal data D.
The new output signal data D is D = D + 2KC. Here, K is a constant, and is given by, for example, an externally provided dip switch or the like in response to the pilot signal level. Currently, K=1/P is set.

Therefore, D =D+2・1/P・(−PD/2)=D+(−D)=0. From this, when the stereo demodulation circuit is started, the output signal data E of the cosine wave calculation circuit 19 is
has a phase difference of D with respect to input signal data A, but as time passes, D = 0, that is, the phase becomes synchronized with input signal data A. Hereinafter, D = 0 will be indicated as D ^* .

Next, a description will be given of what happens after the digital signal processing type PLL becomes synchronized.

The sine wave calculation circuit 21 calculates Qsin(ω ₀ /2nT+D) based on the output data D of the calculation circuit 18, but since D is “0” at D ^* , the output data of the sine wave calculation circuit 21 F becomes F=Qsin(ω ₀ /2nT).

Similarly, the output data of the sine wave calculation circuit 22
G ₁ and the output data G ₂ of the sine wave calculation circuit 23 are respectively G ₁ = 1/2 + sin (ω ₀ nT + 2D ^* ) → 1/2 + sin (ω ₀ nT) G ₂ = 1/2 − sin (ω ₀ nT + 2D ^* ) →1/2−sin(ω ₀ nT).

Here, Q is a constant given so that Q=-P, and is initialized by an externally provided dip switch or the like.

Therefore, the output signal data H of the digital adder 24
is H=A+F =(L+R)+(L-R)sinω _S nT +Psinω _S /2nT +Qsin(ω ₀ /2nT) =(L+R)+(L+R)sinω _S nT where Q=-P, ω ₀ =ω It is _S.

Therefore, as is clear from the output signal data H, the reference pilot signal is completely canceled by the digital adder 24.

The output signal data H of the digital adder 24 is multiplied by the output signal data G ₁ of the sine wave calculation circuit 22 and the output signal data G ₂ of the sine wave calculation circuit 23 in digital multipliers 25 and 26, respectively.

Therefore, the output signal data I ₁ and I ₂ of the digital multipliers 25 and 26 are I ₁ = H×G ₁ = [(L+R) + (L-R) sinω _S nT] × [1/2+sinω ₀ nT] = 1/2 (L + R) + 1/2 (L - R) sinω _S nT + (L + R) sin ω ₀ nT - 1/2 (L - R) cos (ω _S + ω ₀ ) nT + 1/2 (L - R) cos (ω _S −ω ₀ )nT Now, since ω _S =ω ₀ , I ₁ =L+1/2(3L+R) sinω _S nT −1/2(L−R)cos2ω _S nT.

Similarly, I ₂ =R-1/2(3R+L) sinω _S nT +1/2(L-R) cos2ω _S nT.

Output signal data of digital multipliers 25 and 26
Since I ₁ and I ₂ are outputted through the digital low-pass filters 27 and 28, respectively, the output signal data I ₁ and I ₂ are output from the digital filters 27 and 28.
The high frequency components of are removed, and the output signal data of the digital low-pass filters 27 and 28
J ₁ and J ₂ will be stereo demodulated as J ₁ =L J ₂ =R.

In addition, here, the free run angular frequency ω ₀ , its 1/
ω ₀ /2 of 2 and the sampling rate T may be stored in the ROM in advance and output to the cosine wave calculation circuit 19 and the sine wave calculation circuits 21 to 23.

Furthermore, since the reference pilot signal level differs depending on the country, it can be changed by applying it using a dip switch or the like as described above.

Furthermore, sine wave calculation circuits 22 and 24,
If the calculation speed is increased, it is possible to reduce the number to just one by time division. The same applies to the digital low-pass filters 27 and 28.

(Effects of the invention) As explained above, according to the invention, since the stereo demodulation circuit processes all digital data, the occurrence of drift is eliminated and an infinite degree of separation can be obtained.

Furthermore, there is no need to adjust the voltage controlled oscillator, and since no switching is performed, there is an advantage that no interference waves are generated.

Furthermore, by increasing the number of bits of processed data, the S/N ratio is improved, and since the sampling rate is not low as in the sampling and hold method, flatter frequency characteristics can be obtained.

Further, by integrating the circuit, it is possible to reduce the size and save energy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional switching type stereo demodulation circuit. FIG. 2 is a block diagram showing one embodiment of the present invention. 16, 25 and 26...digital multiplier, 1
7, 27 and 28...Digital filter, 18
...Arithmetic circuit, 19...Cosine wave arithmetic circuit, 20...
...Digital signal processing type PLL, 21 to 23...Sine wave calculation circuit, 24...Digital adder.

Claims (1)

[Claims for Utility Model Registration] A digital signal processing type PLL that is supplied with input signal data A obtained by A/D converting a composite signal and outputs phase difference detection output data D, and a phase difference detection output data D from the PLL. is supplied and the pilot signal level in the composite signal is P, ω ₀ is the angular frequency equal to the angular frequency of the subcarrier, n is a positive integer that is increased by 1 for each sample pulse that samples the composite signal, and T is the sampling rate. When, −Psin(ω ₀ /2nT+D), 1/2+sin(ω ₀ nT+2D) and 1/2−sin(
first, second, and third arithmetic circuits that calculate ω ₀ nT +2D); a digital adder that adds the input signal data A and the output signal data of the first arithmetic circuit; a first digital multiplier that multiplies the output signal data of the adder and the output signal data of the second arithmetic circuit; and a first digital multiplier that multiplies the output signal data of the digital adder and the output signal data of the third arithmetic circuit. a second digital multiplier, and first and second digital low-pass filters that receive output signal data of the first and second digital multipliers, respectively. .