JPS5975722A - エクスクル−シブｏｒ回路 - Google Patents

エクスクル−シブｏｒ回路

Info

Publication number
JPS5975722A
JPS5975722A JP18648182A JP18648182A JPS5975722A JP S5975722 A JPS5975722 A JP S5975722A JP 18648182 A JP18648182 A JP 18648182A JP 18648182 A JP18648182 A JP 18648182A JP S5975722 A JPS5975722 A JP S5975722A
Authority
JP
Japan
Prior art keywords
transistor
circuit
level
output
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18648182A
Other languages
English (en)
Japanese (ja)
Other versions
JPS64853B2 (forum.php
Inventor
Masaki Nakai
中井　昌喜
Kiyoshi Nishimura
清 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP18648182A priority Critical patent/JPS5975722A/ja
Publication of JPS5975722A publication Critical patent/JPS5975722A/ja
Publication of JPS64853B2 publication Critical patent/JPS64853B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/212—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using bipolar transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
JP18648182A 1982-10-24 1982-10-24 エクスクル−シブｏｒ回路 Granted JPS5975722A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18648182A JPS5975722A (ja) 1982-10-24 1982-10-24 エクスクル−シブｏｒ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18648182A JPS5975722A (ja) 1982-10-24 1982-10-24 エクスクル−シブｏｒ回路

Publications (2)

Publication Number Publication Date
JPS5975722A true JPS5975722A (ja) 1984-04-28
JPS64853B2 JPS64853B2 (forum.php) 1989-01-09

Family

ID=16189234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18648182A Granted JPS5975722A (ja) 1982-10-24 1982-10-24 エクスクル−シブｏｒ回路

Country Status (1)

Country Link
JP (1) JPS5975722A (forum.php)

Also Published As

Publication number Publication date
JPS64853B2 (forum.php) 1989-01-09

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