JPS5967417A - Waveform recording device - Google Patents

Abstract

PURPOSE:To enable the multiplication of channels in a memory of the same capacity, by providing RAM of one-word one-bit system which selects, as a storage element, one bit of a memory cell located in a position corresponding to each input at every input of sample data. CONSTITUTION:A memory 10 is formed of RAM used according to a one-word one-bit system, and one memory cell is selected from a memory cell array 11 based on the outputs of a line decoder 12 and a column decoder 13. Under the condition, an output P from an operation control circuit 9 is supplied to one input terminal of a control circuit 15, and when the output P is H, writing in the memory cell 11 turns impossible, while it turns possible when said output is L. When a selection switch of the operation control circuit 9 is set for a writing operation and a start switch is closed, the outputs E, F and P of the operation control circuit 9 turn to be H, L and L, respectively. Thereby the memory 10 is set for the writing operation and a switch 29 is closed, whereby a constitution shown in the figure is obtained. As the result, no blank period other than a time required for the conversion by an A/D converter occurs, and thus the multiplication of channels in a memory of the same capacity, as well as X-Y recording, can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform recording device that temporarily stores analog human power in a memory after 7+/D conversion, and records the contents of the memory on a recording paper or the like.

Conventional waveform recording devices that A/D convert analog human input and then store it in memory include wave memories and storage oscillographs. In these devices, when the memory capacity is n words and the recording time is 8 seconds, sampling is performed n/s times/second. At this time, if the sampling time required to convert the analog human power once A/D and store this output as one word in the memory is T, then nT-s (here, the sampling time is A/D).
/D conversion time. ), a recording similar to the input signal is reproduced. However, it suddenly occurred,
In addition, when measuring phenomena with long repetition periods, such as impulse-like noise measurements, a recording time of n T ((s) is required. If such recording is performed, the analog A/D convert the input value and convert it to 1
Although it is stored as a word, the remaining time of s/n T becomes a blank period in relation to the sampling time T mentioned above. FIG. 1 shows the correlation between input and recording in this waveform recording. Here, 7 hours of sampling is performed during the S/N period, and when recording the testimonials, the data from this sampling is output during the S/N period. However, changes in human power during the S/n-T period do not appear in the recorded waveform, resulting in a disadvantage that waveform reproducibility deteriorates.

The present invention was developed in order to improve these drawbacks, and the reproducibility of recording for input is independent of recording time S, is determined only by spring-pulling time T, and is It is an object of the present invention to provide a waveform recording device line that does not require additional memory for channelization and can be extremely easily converted to an XY recorder.

To this end, the present invention treats the recording surface of the waveform recording device as a collection of small dots D. For example, if a recording surface consisting of a square with a side of 10 cm is shifted from one point to a square with a side of 1 mm, there will be a set of ioooo points, but this recording surface has a memory cell array arranged in a matrix similar to the recording surface. By providing a random access memory (hereinafter referred to as "RAM"), each point on the recording surface can be assigned to one memory cell.
By making it compatible with B and G, you can also convert analog human power into A
'/D conversion means for supplying the rope coater 'G;
Means for supplying a pulling force having a relationship of mT-B/n between the sampling time T, the frequency division number m1, the recording time S1 and the number of columns n to the column decoder, and from the output of the row decoder and the output of the column decoder. By providing a means for selecting and storing a memory cell (H), during a write operation, the level of the memory cell hit at the position floor corresponding to each input of sampling data is changed from "Ll' to H" at every sampling time T.
” and write sequentially to memory cell 1 to be recorded.
If sampling data is already in bit and bit and the level is “H”, you can continue writing as is.1
This is a waveform recording device that uses RAM as a word 1-bit format.

The present invention will be described in detail below with reference to the accompanying drawings.

FIG. 2 shows a first embodiment of the basic configuration of the present invention, and is a waveform recording device in which the horizontal axis is the time axis.

In the figure, 1 is an oscillator that generates a clock signal, and 2 is an oscillator that generates a clock signal.
6 is an A/D converter, which will be described later, and a counter for creating a signal to control the write operation of the memory, and 6 is an A/D converter, and originally the conversion method such as successive approximation type or parallel comparison type does not matter, but this In the embodiment, it is a successive approximation type. Reference numeral 4 is a counter for reading the contents written in the memory and controlling the recording, which will also be described later.

5 is a frequency divider; 6 is a frequency division number determination circuit that determines the frequency division number of the frequency divider 5; 7 is a counter that operates in response to the output of the frequency divider; 8 is a circuit that operates the counter 7 when the power is turned on; 9 is an operation control circuit that controls storage of input signals or readout of the storage based on the output of the counter 7 or human operation.

Reference numeral 10 denotes a RAM used as a 1-word 1-bit system, which includes a memory cell array 11, a rote coder 12,
A column decoder 16, a column output circuit 14, and a control circuit 15 that controls writing and reading from memory cells.
etc.

20.21.22.23.24.25.26.27.2
Reference numeral 8 denotes a group of switches for cutting off and on the output signals of the circuits connected to each other, and is controlled by the output of the operation control circuit 9 described above.

A gate group 29 controls the operation of the A/D converter B and writes the output of the A/D converter B to the memory 10 in accordance with the count value of the counter 2.

A recorder part for recording the contents written in the memory 10 includes a recording paper 60', a recording head and head drive section 31, a pulse motor 32, and a motor drive circuit 36.
It is composed of.

40 is a FRI, PUFRO, and B, and 41 is a signal delay circuit.

In this embodiment, counter 2.4 is used to explain the operation.
．． 7, and the A/D converter 6 and memory 10 are all 4 bits,
This will be explained as a default configuration.

FIG. 6 shows an example of the configuration of the operation control circuit 9, which includes a switch 91 for selecting writing and reading, a start switch 92 consisting of a non-opening and rectangular push switch, and a start switch 92. initialized,
The J- type flipflop 93 receives the output of the counter 7 as a clock, and the selection switch 91 and the flipflop.

A gate group 94 for controlling each of the switch groups 20 to 28 according to the output state with the pflop 93, and a time constant circuit 9 for initializing the FRI, PFLO, and PF96 when the power is turned on.
It consists of 5.

In this configuration, when the power is turned on, the J terminals of FRI, BUFLO, and B are held at "L" for a certain period of time by the time constant circuit 95, so that the output Q becomes "L" and is initialized.

As a result of this output, both outputs of F and F become "L" outputs regardless of the state of the selection switch 91. Next, when the start switch 92 is pressed, the output Q changes to "H'" because 7 trips are input, "H" is input to the J terminal of the switch 93, and "L" is instantaneously input to the K terminal of the switch 93.
When it returns to its original state, all of the aforementioned terminals change to "H", so the output of the counter 7 makes it possible to drive the buffer 7 and 9, and furthermore, the output Q changes to "H", so the selection switch 91 Depending on the state, if it is a write operation, the output E will be “H”, and if it is a read operation, the output F will be “H”.
becomes.

When an output is generated from counter 7, Pflo7 93
is inverted, and the output Q becomes °°L'', which returns to the same state when the power is turned on.Furthermore, a signal obtained by inverting the output of the flip-flop 93 is output as the output P.The switch groups 20 to 28 each receive a control signal. If is °H′″, close;
If it is "L'", an opening operation is performed.

Next, the operation of the first embodiment will be described with reference to the fourth to eighth configuration diagrams during writing and reading, respectively.

Figure 4 shows that the output E of the operation control circuit 9 is °゛H'', and the output F is '
This is a configuration diagram in a state where P is "L", that is, a write operation to the memory 10 is possible, and 20, 21, 25, 26, 27 of the control switch group are open. 22, 26, 24, and 28 are in the closed state, and the groups [)] are deleted from the configuration diagram.

FIG. 5 is a timing chart of each part in FIG. 4 showing the operation during the write operation. Note that the shaded area indicates that the data content remains unchanged.

In FIG. 4, the operation of the memory 10 will be explained. As mentioned above, the memory 10 is a RAM used in a 1-word, 1-bit format, and the memory cell array 11 is, for example, a 16×16 matrix for 4 bits. It consists of In the memory cell array 11, one memory cell is selected by the outputs of a row decoder 12 and a column decoder 13. When the memory cell is selected, the output P of the operation control circuit 9 is supplied to one input terminal of the control circuit 15, and if this output P is H'', the memory cell 11
It becomes impossible to write to or read from 'L”
', then writing or reading is performed by a signal applied to the other terminal of the control circuit 15.

In this configuration diagram, the output P of the operation control circuit 9 is "L"
The signal applied to the other terminal of the control circuit 15 is
Writing is performed at "L", and reading is performed at "H". At the time of writing, the state of the output of the delay circuit 41 is written.

When the power is turned on now, the outputs of the operation control circuit 9 are as described above: the output E is 'L', the output F is L'°, and the output P is 'H'.
In this state, the count value of the counter 7 is set to zero by the initialization circuit 8, and the switch 28
is open, so the counting operation is stopped. Next, the selection switch 91 of the operation control circuit 9 is set to the write operation, and the start switch 92 is closed. As for each output of the operation control circuit 9, the output E is 'H', the output F is 'L''', and the output P is ”
LOW”, the memory 10 performs write operation, switch 28
is closed, resulting in the configuration shown in FIG.

The means for A/D converting the analog input and supplying it to the row decoder of the memory 10 sequentially performs the following operations.

Here, a counter 2 that runs freely by the output of the oscillator 1
generates a BOD code output in accordance with the J1 value, and in this embodiment is an octal counter in which the circuit of counter 2 operates when the output of D changes to H.

Game when the j1 value of counter 2 becomes zero) 1!
A/D conversion command from 'I 29' (29 in Figure 5)
-1) is issued. The successive approximation type A/D converter 6 digitizes the analog data 16 applied to the input terminal 5' according to this conversion command. At this time, the lower bits are sequentially converted every clock from the most significant focus (MSB) by the clock signal from oscillator 1, and 4 clocks after the conversion command is generated.
After completing the bit conversion, the row decoder 12 of the memory 10
supplied to

The means for supplying the time measurement input having the relationship m T = s / n between the sampling time T, the frequency division number m, the recording time S, and the number of columns n to the column decoder 13 of the memory 10 is as follows. The operations are performed sequentially.

The frequency dividing circuit 5 is a frequency dividing circuit operated by the D code output of the counter 2, and its frequency division number corresponds to the sampling time T shown in the frequency division number method, and the frequency division number m of the frequency dividing circuit and the sampling time The time Tm multiplied by T corresponds to s/n. Note that n is the number of columns and is equal to the capacity n words. Therefore, when the recording time and day are determined, m = s
The frequency division number is /nT. Counter 7 is initialization circuit 8
After the count value is set to zero, the count value is advanced by the output from the frequency dividing circuit 5. The BOD code output of the counter 7 is supplied to a column decoder 13 of a memory 10.

The means for selecting one memory cell from the outputs of the row decoder 12 and the outputs of the column decoder 16 and performing writing sequentially performs the following operations.

Gate group 29 is the fifth gate when the count value of counter 2 is 6 and 7.
The output 29-2 shown in the figure is generated, and this output is inverted and then transmitted to the memory 10 at the "H" level via the delay circuit 41. When the output of gate nl 29 to 29-2 is generated, the A/I) conversion has been completed and the digital value corresponding to the analog human input value is supplied to the row decoder 12, and the count value of the counter 7 is supplied to the column decoder 13. One of the memory cell arrays 11 is selected by the matrix and the output from the gate group 29 is sent to the control circuit 15 of the memory 10.
Manually input "L" to the other input terminal to start writing operation.

At this time, the output level of the delay circuit 41 is written in the selected cell. Here, the delay circuit 41
Since it is necessary to maintain a predetermined level until the memory 10 finishes the write operation, a delay time t is generated to stabilize the write data.

In response to the inversion of the D code signal when the counter 7 completes one count and returns to the initial value, each output of the operation control circuit 9 is output E.
is "L", the output F is returned to "L", and the output P is returned to "H", thus completing the write operation.

FIG. 6 is a diagram showing the state of writing into the memory 10 by this write operation and the corresponding state of recording on the recording surface. Note that diagonal lines in the memory cell array 11 indicate writing.

In the figure, the A/D converter operates every one word period of the counter 2, and this one word period is T. Frequency dividing circuit 5
The frequency is divided by 115, and the counter 7 is operated by this output, so that it is s/n-5T. For this reason, the output of the column decoder 13 to which the output of the counter 7 is connected does not change until A/D conversion is performed five times, and the memory cell array 11 remains fixed with one side of the matrix determined by the column decoder 16 being A/D. Writing to the memory cell array 11 selected by the output of the row decoder 12 determined by the output of the /D converter 3 is repeated five times. Therefore, even if there is a sudden change in the input signal, the Memo IJ 101
11"L is inserted into the

Next, the reading operation and recording of data written in the memo IJ 10 by the writing operation described above with reference to FIGS. 7 and 8 will be described.

In FIG. 7, each output of the operation control circuit 9 shifts to a read operation, and the output E is L'', the output F is "'H",
The output P becomes 'L'. In this state, the switches 20, 21, 25, 26, and 27 are closed in the switch group shown in Figure 2.
Since switches 22, 23, 24, and 28 are opened, these switches have been omitted from the drawing.

Referring to Figures 4 and 5, 1chi! In the write operation described above, when the counter 7 completes one counting cycle, each output of the operation control circuit 9 returns to its initial state.
As described above, in this state, the counter 4 is initialized to zero, and the flip-flow knob 40 is also initialized.

Further, the counter 7 also returns to zero and remains in an immovable state.

First, the selection switch 9 of the operation control circuit 9 shown in FIG.
1 is selected on the read side and the start switch 92 is closed, each output of the operation control circuit 9 enters the aforementioned read state, and the counter 4, FRI, BUFLO, and P40 become operable. The counter 4 receives the output of the oscillator 1 and advances the number by 4, and when one counting period ends, the output of the Pflosob 40 is inverted in response to the falling edge of the D code output of the counter 4. Furthermore, when one word cycle of counter 4 ends, the output of 7 lips 70 tongues 40 returns to the original position.
In response to this inversion of the output, the count value of the counter 7 is incremented by one. In other words, in 281 cycles of counter 4, counter 7
The count value of is incremented by one.

Incidentally, FIG. 8 shows the operation timing of each part during two counting periods of the counter 4.

During the first counting period of the counter 4, the output of the flip-flop 40 remains at 'L', and the gate 42 to which this output and the output of the oscillator 1 are added remains fixed at 'H'' during this period. .

The output of this gate 42 is inputted to the other terminal of the control circuit 15 of the memory 1o, and the memory IJ 10 is connected to the memory cell array 1.
The contents of 1 can now be read.

Here, when the B1 value of counter 4 advances, counter 7
Since its count value is still zero, counter 4 is 3.
The first row in the IJ wax of the memory cell array 11 is sequentially read out according to the numerical value. If there is something written as "'H" in the memory cell, a "'H" output is generated.

The output of the gate 42 is also applied to the gate 4, and the gate 43 is connected to the developed oscillator 1 where the output of the gate 42 is °'H°°.
generates a signal similar to the output of

The output of gate 46 is further fed to gate 44,
The output of the memory 10 is applied to the other human input terminal of the gate 44. Therefore, the output of the memory 10 is 'H' while the output of the gate 43 is 'H'.
This is to sequentially scan the addresses of the memory cell array 11 ゛ . This is to remove portions where the data content is uncertain, such as between 111j of the address set.

When the counter 4 completes the first few cycles, the output of the flip-flop 40 changes to ``°H'', and the output of the gate 42 is connected to the oscillator 1 connected to the other human input terminal.
The appearance of the opposite phase of is shown. When the output of the gate 42 turns to L°, the control circuit 15 of the output memory 10 puts the memory 10 into a state where a write operation can be performed, and the output of the delay circuit 41, to which the output of the gate 42 is simultaneously added
Memory cell array 11 of memory 1o di:11
1m &"L" level is written and refreshed. Here, the reason why the output of the gate 42 performs the write operation by the output of the oscillator 1 and the output of the opposite phase is as follows.
Since the address of the memory cell array 11 of the memory 1o is determined by the counter 4 in the same manner as in the write operation described above, the purpose is to secure sufficient access, door, and write times.

While the memory 10 is being refreshed and refreshed by this write operation, the output of the oscillator 1 is supplied to one input terminal of the gate 43, and the output of the gate 42 is supplied to the other input terminal of the human power E, so that the human power is The phase is reversed, and the output of the gate 43 remains fixed at "L"', and in response, the output of the gate 44 also remains at °L'.In this way, the counter 4 starts the next counting cycle. When the word value is completed, the output of the flip-flop 40 is inverted, so the 81 value of the counter 7 advances by one, and the memory cell array 11 corresponding to this word value is incremented by one.
A read operation for one row is started, and the above-described operations are sequentially repeated.

Next, the relationship between the recording δ1 portion shown in FIG. 7 and the read operation described in 011 will be explained.

As shown in Fig. 2, the recorder section includes recording paper 3d, recording, do and -, do drive unit filter 1, bar/l/smoke 3
2. It is composed of a motor drive circuit 33.

The motor drive circuit 33 has a drive signal and a flip-flop.
The pulse motor is driven by the output of the pulse motor 40 and is controlled in synchronization with the count value of the counter 7 so as to feed one line of recording paper every time the count value of the counter 7 advances by one count. Note that the output F of the motor drive circuit 3 and the operation control circuit 9 is "L".
′ is kept in an inoperable state.

Next, the recording/do drive unit 1 will be explained.

To explain the recording method of this recorder section in this embodiment using thermal recording, the decimal evolution decoder 64 receives the argument output of the counter 4, and the transistors 35 to 35
Any one transistor during the period up to ' is sequentially selected in accordance with the count value of the counter 4. Here, the number of transistors is the same as the total number of bits included in the number of memory cells in one row of the memory 10.

A heat generating resistor 66 is connected to each transistor at 36 degrees, and this resistor generally corresponds to 37' from the drawer.

The transistor 8 has these heating resistors 66 to 66.
When the output of the gate 44 reaches °゛HH, it becomes possible to conduct electricity, and at this time, one of the transistors 65 to 65 corresponding to the count value of the counter 4 can also be energized. By this operation, the selected recording head is heated and the corresponding head portion of the recording paper filter O' develops color.In this way, each time the 81 value of the counter 7 advances by one, the recording paper advances one line. The first counting period of the counter 4 is recorded, and when one counting period of the counter 7 ends and the D hood output of the counter 7 is inverted, the operation control circuit 9 returns to its initial state, that is, each output is changed to the output E. ”L
"', the output F goes to '°L', and the output P goes to 'H°', and the recording operation ends. Note that a recording diagram for this recording operation is also shown in FIG. 6.

Although the waveform recording device using time transport has been described as the first embodiment of the present invention, in this embodiment, a multi-channel manual waveform recording device can be constructed without increasing the capacity of the memory 10.

FIG. 9 shows a second embodiment of the present invention, which is a two-channel waveform recording device.

In the figure, an oscillator 1, a counter 2, a gate group 29,
The structure and operation of the A/D converter 6 and the switch group 22 are the same as those in the first embodiment of the present invention shown in FIGS. 2 and 4, but a plurality of analog inputs are In this embodiment, as means for converting and supplying the converted signal to the low-tecoder, an A/D converter 50 for the second channel is used.
, switch groups 51 and 52 for switching and outputting the outputs of the A/D converter 6 for the first channel and the A/D converter 50 for the second channel, and D of the counter 2.
operates upon receiving the code output, and the two switches n
Flip-flop o for switching between 51 and 52 alternately,
, F53 has been added.

To explain the operation in this embodiment, the initialization of the flip-flop 56 is controlled by the output E of the operation control circuit 9, and if each l block of the operation control circuit 9 now performs a write operation, 7 flips 70 and 7 flips 70, One of the outputs is set to ゛H power due to initialization. If we now make one of these kings,
Switch group 52 is 71J, switch 4. Channel HY51 is open, and first, the A/D converter power for the first channel is written by the write operation shown in FIGS. 4 and 5. After that, when the other output M of the flip-flop 56 changes to H"" by the D code output of the counter 2, the switch group 52 is opened and the switch 51 is closed, so the output of the A/D conversion k 50 of the second channel/11 is changed by the write operation described above. Here, counter 2 requires two word cycles to perform the above operation, but since the output is output from frequency divider 5 onward, the count of counter 7 does not advance and the count does not advance in the same column address. Information on the first channel and the second channel is written. The read and write operations are the same as in the first embodiment shown in FIGS. 7 and 8. Note that it is clear that the present invention can be implemented for the third channel and above, and a description thereof will be omitted.

FIG. 10 shows a configuration diagram during a write operation for performing XY recording as a sixth embodiment of the present invention.

In this embodiment, the output of the counter 7 is connected to a switch group 54, and the output of the counter 7 or the output of the A/D converter 50 of the second channel is connected to the switch group 54 as the column decoder of the memory 10. Either one is input via 51. Note that the switch group 51 is closed during a write operation, and the switch group 54 is closed during a read operation.

During a write operation, the output of the A/D converter 50 of the first channel is input as the row decoder input, and the output of the A/D converter 50 of the second channel is input as the column decoder input, and the input values are set to the respective input values. One memory cell bit in the memory cell array 11 is selected.

The recording time S is determined by the frequency divider 5 and the counter 7, and ends when the counter 7 outputs the D code.

During the read operation, the switch group 54 is closed, so the seventh
The configuration and operation shown in FIG. 8 and FIG. 8 are used.

In each of the above-mentioned embodiments, the memory cells are refreshed during the read operation, but this operation is configured to be started by human operation, and the read and record operation is performed multiple times as necessary. It is also extremely easy to do so, and it is obvious that various measures can be taken not only for the recording method such as thermal recording or discharge recording for the recorder part, but also for its operation method.

Furthermore, it is extremely easy to replace each control circuit, switch group, etc. in each embodiment of the present invention with a microcomputer and its software, and it is possible to arrange memory addresses in a matrix or box shape using a computer program, and to It is also clear that microcomputers and their software are superior in terms of miniaturization and ease of assembly.

As explained above, according to the present invention, not only no blank period other than the conversion time of the A/D converter occurs, but also multi-channel and X-Y recording operations can be performed with the same memory capacity. This has the advantage that a waveform recording device that can be used at a low cost can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the correlation between input and recording in conventional waveform recording. FIG. 2 is a first embodiment showing the basic configuration of the present invention, and is a diagram showing a waveform recording device in which the horizontal axis is the time axis. FIG. 6 is a diagram showing a specific example of the configuration of the operation control circuit in the first embodiment. FIG. 4 is a configuration diagram when a write operation to the memory becomes possible in the first embodiment. FIG. 5 is a timing chart of each part during writing in the first embodiment. FIG. 6 is a diagram showing the writing state to the memory and the corresponding recording state to the recording surface at the end of the writing operation in the first embodiment. FIG. 7 is a configuration diagram during memory read and write operations in the first embodiment. FIG. 8 is a timing chart of each part of the counter 4 during two cycles in the first embodiment. FIG. 9 is a second embodiment of the present invention, which is a partial configuration diagram of a two-channel waveform recording device during a write operation. FIG. 10 shows a sixth embodiment of the present invention, and is a block diagram at the time of writing 1Δ operation for performing XY recording. 1..., clock signal generator 2 pass counter 3'=
A/D converter 5° frequency divider circuit 7°゛counter 9... Operation control circuit 10°゛RAM
11・°Memory cell array 12=,,0-de″-da
13. ,, Column decoder 15... Control circuit
29...Gate group 41°° Signal delay circuit 5
0.-A-D converter 53...Flip 70. Figure 1 Figure 3

Claims (1)

[Claims] 1. In a waveform recording device that converts analog human force into A/D and then temporarily stores it in a memory, and records the stored contents of the memory on a recording paper, etc., in a matrix or box shape. It has a memory cell array, and is equipped with a RAM which is used as a 1-word, 1-bit method, in which 1 bit of the memory cell at a position corresponding to each input of the sampling time data is selected as a storage section. Waveform recording device ff. 2 In a waveform recording device that temporarily stores analog input in a memory after A/D conversion, and records the stored contents of the memory on recording paper, etc., the memory cell array arranged in a matrix or box shape and the column position of the matrix or box The RA has a row decoder that determines the row position of the matrix and a column decoder that determines the row position of the matrix, and is used as a one-word, one-bit system.
A timer having a relationship of m T = s / n between M, a means for A/D converting analog input and supplying it to the rotary decoder, sampling time T, frequency division number m, recording time S, and number of columns n. A waveform recording device comprising means for supplying an input to a column decoder, and means for selecting and storing one bit in a memory cell from the output of the row decoder and the output of the column decoder. (b) In a waveform recording device that A/D converts analog input, temporarily stores it in a memory, and records the memory contents on recording paper, etc., the memory cell array arranged in a 7-trinox shape, the matrix, and the column positions of the boxes are The RA has a row decoder for determining the row position of the matrix and a column decoder for determining the row position of the matrix, and is used in a 1-word, 1-bit system.
m T between M, means for A/D converting each of the plurality of analog inputs and supplying them to the row decoder, sampling time T2 frequency division number m1 recording time s1 and number of columns n
A waveform recorder comprising means for supplying a clock input having a relationship of =s/n to a column decoder, and means for selecting and storing one bit in a memory cell from the output of the row decoder and the output of the column decoder. Device. 4 In a waveform recording device that temporarily stores analog input in a memory after A/D conversion and records the memory contents on recording paper, etc., determines the column position of the memory cell array arranged in a matrix or box shape. The RA has a row decoder that determines the row position of the matrix and a column recorder that determines the row position of the matrix, and is used as a one-word, one-bit system.
M, means for A/D converting the first analog input and supplying it to the row decoder, means for A/D converting the second analog input and supplying it to the column decoder, an output of the row decoder, and an output of the column decoder. A waveform recording device comprising means for selecting and recording 1 bit of a memory cell.