JPS596652A - Differential logical circuit - Google Patents

Abstract

PURPOSE:To obtain logical conversion information from remaining output terminals of a storing element by applying a 2<n>-notation input code and a code obtained by delaying a part of a code obtained from a data output terminal. CONSTITUTION:OR conversion information obtaining any transmission line code array out of a natural code array, a Gray code array, and a rotationally symmetrical code array and the storing element 21 in which information to be operated for the transmitted input codes is written are provided. Binary input codes in four sequences are inputted to the address terminals A0-A3 of the element 21 through input terminals 23 and binary transmission codes of four sequences which are OR-converted and outputted from the output terminals D0-D3 of the element 21 are sent to output terminals 24. Information from output terminals D4-D7 is supplied to the address terminals A4-A7 of the storing element 21 through an one-bit delay element 25.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is used in a communication system that transmits information using differential phase modulation such as digital phase modulation or gauge digital amplitude phase modulation, and converts an input signal into a transmission line signal. The present invention also relates to a differential logic circuit that performs the inverse conversion.

<Prior Art> When transmitting a signal using digital phase modulation, since it is difficult to transmit the absolute phase, the signal is transmitted by giving information to the phase difference between carrier waves. This is called a differential logic method. On the transmitting side, the phase of the carrier wave currently being transmitted is added to the phase of the information to be transmitted next, and the next phase is determined based on this result. On the receiving (K side), the difference between the phase of the carrier wave currently being received and the phase of the carrier wave to be received next is calculated, and this result is used as output information. A differential logic circuit is used to perform a logical operation between pieces of digital information corresponding to the phase of a carrier wave, rather than directly calculating the difference. A transmission logic circuit for converting a binary input code into a binary transmission line code, and a transmission logic circuit for converting the transmitted 2n-ary transmission line code into a binary output code corresponding to the original 2-digit code. This is a general term for receiving logic circuits.

FIG. 1 shows a conventional differential logic circuit used in a four-phase phase difference keying system (4PSK), in which A is a transmitting logic circuit and B is a receiving logic circuit. That is, as shown in FIG. 1A, transmission i! 1iii logic circuit has two sets of binary input codes a1
, ag is a flip-flop FFl.

Flip-flop FFi is read into FFg by a timing signal from terminal 11 and is delayed by 1 bit.

The transmission line codes S, m-1, b, and m-1 outputted one bit (timing signal) ahead of the input code are respectively read into FF4, and these flip-flops FF1 to F
Between the outputs of F4, NOR circuits 1a to 1hXoR circuit 2a
, 2b performs a summation logic operation modulo 4, and the phase of the carrier wave is changed based on the information bl rbR of the operation X result. Furthermore, as shown in FIG. 1B, in the receiving logic circuit, the two sets of binary transmission line codes C1+0g are read into the flip-flops F F s and F' Fs by the timing signal at the terminal 12, and the output from the flip-flops is It is read into seven lip flops FFY and FFs for 1-bit delay. NOR circuits 4a to 4h operate between the input transmission line code and the transmission line code cl, (4g) obtained 1 bit in advance.

The OR circuits 5a and 5b perform a differential logic operation modulo 4, and output the results al and ag.

In addition, Figure 2 shows the 16-value orthogonal width variable method (16QAM).
used for. In the differential logic circuit using a read-only memory (ROM), A in the same figure shows a transmitting logic circuit, and B in the same figure shows a receiving logic circuit. That is, as shown in FIG. 2A, the transmission logic circuit has four series of binary input codes as + a m + j.
L s T Jl 4 and the transmission line code bl rbR1bs , b which is outputted 1 bit ahead of the input code via the 7-bit flip-flop 7 for 1-bit delay.
A summation logic operation modulo 4 of 92 sets in the ROM 8 is performed between 4 and 4, and the amplitude and phase of the carrier wave are changed based on the output information of this operation.

In addition, as shown in FIG. 2B, the reception logic circuit has 4M columns O
2IA Transmission line code “j Cs” + C* ms c
II ``t e 4 '', the transmission line code c1m''''1. ．． m-1,, m-
1.04m''''1, a differential logical operation using 2m modulo 4 is performed by RONlo, and the result is output as information. This 16QAM differential logic circuit can be constructed in the same way even if two sets of 4PSK differential logic circuits shown in FIG. 1 are used.

In this way, in conventional differential logic circuits, the logic operation part is implemented using gate elements or ROM, but the circuit configurations are different for the transmitting logic circuit and the receiving logic (2) circuit. .

<Summary of the Invention> An object of the present invention is to provide the same transmitting logic circuit and receiving logic circuit.
An object of the present invention is to provide a differential logic circuit having a circuit configuration.

According to this invention, the logic operation portion of the differential logic circuit is provided with a memory element in which logic conversion information according to the logic conversion rule modulo 2n is written in advance, and the address input terminal of this memory element is provided with a 2n-base input. By adding a code or a 2n-ary transmission line code and a code obtained by delaying a part of the code m from the data output terminal of the memory element by 1 bit, the logic conversion information is output to the remaining data output terminal of the memory element.・Ra ru.

<Embodiment> FIG. 3 is an embodiment of the present invention, showing a differential logic circuit for 16QAM system. First, to explain the case where FIG. 3 is used as a transmission logic circuit for the 16QAM system, a summation logic that can obtain a transmission path code constellation of either a natural code constellation, a gray code constellation, or a rotationally symmetric code constellation. The conversion information and the operand information for the transmitted input code are
A storage element 21 containing k'@ is provided. The 4-series binary input code a, m, a, m, , m, 84m is input terminal 2.
3 to the address terminal AoAIAff of the storage element 21.
Each is input to iAs. The output terminal D of the memory element 21 (the sum of IDIDzDs and si!!) is the converted four-series binary transmission W'r code bx", bs+-, bsm,
b4mtri output m24K sent. The output of the output terminal D 4 D s D mD7 of the memory element 21 is passed through the 1-pit delay capacitor 25 to the address terminal A 4 A s A s A ? is input.

The storage element (ROM or RAM) has 8 series address input terminals AO-A? and 8 series data output terminals DO~D
7 and has a storage zero value of 2048 bits or more.

FIG. 4 shows an example of a truth table according to the summation logic conversion rule in this circuit. The transmission input codes a1m, a2m, a are set in advance so that the address input code AoxAy in the left column of FIG.
8m, 84m and 1-pit delayed operand codes, that is, transmission line codes b1m-1, b2m outputted 1 bit in advance
-1, b8m-1, b4m-1 Summation logic conversion information b1m, b, m for noshateno input conditions.

bam and b4m are generated and stored in the memory element 11 so as to become the upper 4 bits and lower 4 bits of the data output. As a result, the transmitted input code of the input terminal 23 and the operand code obtained via the 1-bit delay multiplier 25, that is, the 1-bit delay transmission line code, are transferred to the address input terminal A of the storage element 21.

~By adding to A7, the sum corresponding to the input sign,
The logical change information and the operand information are obtained at the data output terminals Do=D and D4 to D of the storage element 21.

In addition, the transmission line code and operand/1 code 1 Yl in Figure 4
rn(blrn,bgm)Ylrrl(b-1to4m)
C, Transmission input code X, m(,,m,,,m),x,m(
a, m, 84m) and 1 bit slow 1MM31EFLj
+Yxm-”(b+”-1, b--”).

Yg"-"(btm-", bgm-") wof L/
--Convert to Sf leek, ri6t, Yt"=(Xsm+Y
sm-”) M OD 4 and Ygrn=(X/”
+Yg"-") MOD 4 Wott'll L, Tem
This value is obtained by further natural-gray conversion of the tL value, and the transmission line code arrangement follows the '1AiI logical conversion rule, which results in a natural code arrangement. fc, gray〇natural and natural-gray conversion need not be performed.

Next, to explain the case where FIG. 3 is also used as a reception logic circuit for 16QAM system, the storage element 21 stores the transmission path code of natural type code arrangement, gray type code arrangement & or rotationally symmetric code arrangement as the original transmission input. Rounding difference conversion information to be converted into a reception output code corresponding to the code and operand information for the reception transmission line code are written, and input terminal 2
3 has the transmission line code c 1”, (!2”, cmm,
The output terminal 24 that receives the 04m input receives the differential logic-converted reception output ``1, sign, ・sign atm, at'', asm, 8.
4m is obtained.

An example of a truth table according to the differential logic conversion rule in this circuit is shown in FIG. Transmission line codes c1m, c2m, ca are set in advance so that the address input code Ao-yAt in the left column of FIG. 5 becomes the data output code Do-07 in the right column.
m, 04m and the 1-bit delayed operand code, that is, the transmission line code c1m obtained 1 bit ahead of the transmission code.
``''Difference logic conversion for all input conditions of t, c, m-1, c, m-1, 84m-1, Conversion 1. ．． information a1
m, , m, a, m, 84m are created and used as the upper 4 bits of the data output, and the transmission line codes C1m, C2m, C
8m and 04m are stored in the storage element 21 as they are as the lower 4 bits of the data output. As a result, the transmission line code of the input terminal 23 and the operand code obtained via the 1-bit delay element 25, that is, the 1-bit delayed transmission line code, are transferred to the address input terminals AO-A? of the storage element 21. By adding the differential logic conversion information and operand information corresponding to the transmission line code to the data output terminal D of the storage element 21,
Obtained in O~D8 and D4~English]7. In addition, as in Figure 4, VCM 5 (D receiver 4g IJJ code XIm (a -, axrn), Xsm (aa" + a4
m) 'd Transmission line code sm (cl" + c2"), Z
Transmission line code Ztm-” (c1'-', asm-") +
After converting Zsm-"Canm-" +904m-1) to gray fist natural, X t "-(Z t "Z
t ”-') M OD 4 and D x2”-(Z
2mZ2"-") IVIOD 4 is further converted into natural gray. However, it is not necessary to perform gray-natural and natural-gray conversions.

A transmission logic circuit that writes such summation logic conversion information and operand information into a storage element, and a difference! If the reception logic circuit in which the 1fiI physical conversion information and the operand information are written in the storage element is used for the transmission (Ill) and reception side of the same transmission path, and no vA error occurs on the transmission path, the above 16QAM method is used. In the case of blm, bl!m,
b, m, b, m C, m, CIIm, C, m,
If C and m are equal, a received output code matching the transmitted input code can be obtained.

FIG. 6 shows a general configuration of a 2n-ary differential logic M path to which the present invention is applied. Summation logic conversion information and operand information modulo 2n or differential logic conversion information modulo 2n and operand information The input code from the 21-decimal code input terminal 33 is input to the address A o =An -+ of the memory search element 31, The output D o =D n-1 of the memory search element 31 is the 2n-ary logic conversion code output terminal 3
4. Output Dr of memory search element 31, ~D2n-
t is supplied to the address terminals An to A2n-1 of the storage element 31 through the 1-bit delay element 32.

<Effects> As explained above, according to the present invention, the same code as the remaining data output is output to a part of the data output terminal of the memory element used in the differential logic circuit, or the input transmission line code is By outputting the same code as , it can be used as a transmitting logic circuit or a receiving logic circuit. Therefore, a transmitting logic circuit or a receiving logic circuit can be realized with the same circuit configuration only by changing the storage element. Therefore, if this invention is used, #! It is possible to reduce the cost of design.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a conventional 4PSK differential logic circuit;
Figure 2 shows 16QA using conventional memory access memory (ROM).
FIG. 3 is a diagram showing an embodiment of the differential logic circuit for the 16QAM method using the present invention, and FIG. 4 is a diagram showing the differential logic circuit for the M method according to the summation logic conversion rule of the present invention. FIG. 5 is a diagram showing an example of a truth table, FIG. 5 is a diagram showing an example of an X-logical table according to the differential logic conversion rule of the present invention, and FIG. 6 is a diagram showing the general configuration of a differential logic circuit according to the present invention. It is a diagram. 21.31: Memory element, 23, 33: Code input terminal, 24, 34: Logic conversion code output terminal, 25.32:1
Bit delay element. Patent Applicant: Nippon Denbutsu Denkintsu Corporation Agent: Bei Kurumano

Claims (1)

[Claims] (1) In a differential logic circuit that converts a binary input code into a binary transmission line code and converts the transmission line code into a 2n output code corresponding to the original 2n input code, a memory element in which logic conversion information is written in accordance with a logic conversion rule that is a modulus; a binary input code or a binary field path code;
By adding a code obtained by l-pit delay to a part of the code obtained from the data output terminal of the memory element, logic conversion information is obtained from the remaining data output terminal of the memory element, and address input is obtained. The differential logic circuit wherein the memory element is configured such that the code of the data output terminal to be fed back to the terminal is the same as the binary body transmission path code.