JPS6347388B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is used in a communication system that transmits information using differential phase modulation such as digital phase modulation or digital amplitude phase modulation, and converts an input signal into a transmission line signal. This invention relates to a differential logic circuit that performs the inverse conversion.

<Prior art> When transmitting a signal using digital phase modulation, since it is difficult to transmit the absolute phase, the signal is transmitted by giving information to the phase difference of carrier waves. This is called a differential logic method, and on the transmitting side, the phase corresponding to the information to be transmitted next is added to the phase of the carrier wave currently being transmitted, and the next phase is determined based on this result. On the receiving side, the difference between the phase of the currently received carrier wave and the phase of the next received carrier wave is calculated, and this result is used as output information. These operations are performed using differential logic circuits to perform logical operations between digital information corresponding to the carrier wave phase, rather than directly calculating the sum or difference between the carrier wave phases. There is. This differential logic circuit includes a transmission logic circuit for converting a 2n ^- ary input code into a ^2n- ary transmission line code, and a transmission logic circuit for converting a ^2n-ary input code into a 2n-ary transmission line code, and a transmission logic circuit for converting the transmitted 2n-ary transmission line code to the original 2n ^-ary input code.
It is a general term for the receiving logic circuit for converting into ²ⁿ output codes.

FIG. 1 shows a conventional differential logic circuit used in a four-phase phase difference keying system (4PSK), in which A is a transmitting logic circuit and B is a receiving logic circuit. In ^other words _{, as shown} in ^FIG _.
is read by the timing signal from terminal 11, and the flip-flops FF ₃ and FF ₄ for 1-bit delay are read.
Then, the transmission line codes b ₁ ^m-1 and b ₂ ^m-1 outputted one bit (timing signal) ahead of the input code are respectively read, and these flip-flops FF ₁ to
Between the outputs of FF ₄ , NOR circuits 1a to 1h and OR circuits 2a and 2b perform a summation logic operation modulo 4, and the phase of the carrier wave is determined by the information b ₁ ^m and b ₂ ^m of the operation result. It's changing. In addition, as shown in FIG. 1B, the reception logic circuit has two sets of binary transmission line codes.
c ₁ ^m and c ₂ ^m are flip-flops FF ₅ and FF ₆ connected to terminal 1.
The flip-flop is read with the timing signal of
Read into FF ₇ and FF ₈ . The transmission line code c ₁ ^m-1 obtained by preceding the input transmission line code by 1 bit,
NOR circuits 4a to 4h and OR circuit 5 between c ₂ ^m-1
A and 5b perform a differential logical operation modulo 4, and the results a ₁ ^m and a ₂ ^m are output.

Further, FIG. 2 is used for a 16-value quadrature amplitude modulation method (16QAM). In the differential logic circuit using a read-only memory (ROM), A in the figure shows a transmitting logic circuit, and B in the same figure shows a receiving logic circuit. That is, as shown in FIG. 2A, the transmission logic circuit receives four series of binary input codes a ₁ ^m , a ₂ ^m , a ₃ ^m , and a ₄ ^m and receives 1 bit from the input code via a flip-flop 7 for a 1-bit delay. Transmission line code b ₁ ^m-1 , b ₂ ^m-1 ,
Two sets of summation logical operations modulo 4 are performed between b ₃ ^m-1 and b ₄ ^m-1 by the ROM 8, and the amplitude and phase of the carrier wave are changed based on the output information of this operation.

In addition, as shown in FIG. 2B, the receiving logic circuit has four
The binary transmission line codes of the series c ₁ ^m , c ₂ ^m , c ₃ ^m , c ₄ ^m and 1
Transmission line code obtained one bit ahead of the input code via bit delay flip-flop 9
ROM10 between c ₁ ^m-1 , c ₂ ^m-1 , c ₃ ^m-1 , c ₄ ^m-1
A differential logic operation modulo 4 is performed on two sets, and the result is output as information. this
The 16QAM differential logic circuit is 4PSK as shown in Figure 1.
A similar configuration can be achieved by using two sets of differential logic circuits.

As described above, in conventional differential logic circuits, the logical operation portion is realized by gate elements or ROM, but the circuit configurations are different between the transmitting logic circuit and the receiving logic circuit.

<Summary of the Invention> An object of the present invention is to provide a differential logic circuit in which a transmission logic circuit and a reception logic circuit have the same circuit configuration.

According to this invention, the logic operation portion of the differential logic circuit is provided with a memory element in which logic conversion information according to the logic conversion rule modulo ^{2 n} is written in advance, and the address input terminal of this memory element is connected to the address input terminal of the memory element. By adding the input input code or the ^2n- ary transmission line code and a code obtained by delaying a part of the code obtained from the data output terminal of the memory element by 1 bit, the logic conversion information is converted to the remaining data of the memory element. Obtained from the output terminal.

<Embodiment> FIG. 3 is an embodiment of the present invention, showing a differential logic circuit for 16QAM system. First, to explain the case where FIG. 3 is used as a transmission logic circuit for a 16QAM system, an integration logic that can obtain a transmission path code constellation of either a natural code constellation, a Gray code constellation, or a rotationally symmetric code constellation. A storage element 21 is provided in which conversion information and operand information for the transmitted input code are written. 4 series binary input code
a ₁ ^m , a ₂ ^m , a ₃ ^m , and a ₄ ^m are respectively input to the address terminal A ₀ A ₁ A ₂ A ₃ of the storage element 21 through the input terminal 23 . Four series of binary transmission line codes subjected to summation logic conversion from the output terminal D ₀ D ₁ D ₂ D ₃ of the memory element 21
b ₁ ^m , b ₂ ^m , b ₃ ^m , and b ₄ ^m are sent to the output terminal 24 . The output of the output terminal D ₄ D ₅ D ₆ D ₇ of the storage element 21 is inputted to the address terminal A ₄ A ₅ A ₆ A ₇ of the storage element 21 through the 1-bit delay terminal 25. The storage element (ROM or RAM) has 8 series address input terminals A ₀ to A ₇ and 8 series data output terminals D ₀ to _{D 7} , and has a storage capacity of 2048 bits or more.

An example of a truth table according to the summation logic conversion rule in this circuit is shown in FIG. The transmission input codes a ₁ ^m , a ₂ ^m , a _{3 m} ^, a are set in advance so that _the address input codes A ₀ to A ₇ in the left column of FIG. ₄ ^m and 1-bit delayed operand code, that is, all input conditions of transmission line codes b ₁ ^m-1 , b ₂ ^m-1 , b ₃ ^m-1 , b ₄ ^m-1 outputted 1 bit in advance. Integration logic conversion information for b ₁ ^m , b ₂ ^m , b ₃ ^m ,
Create b ₄ ^m and store it in the memory element 11 so that it becomes the upper 4 bits and lower 4 bits of the data output.
Remember it. As a result, the transmitted input code of the input terminal 23 and the operand code obtained via the 1-bit delay terminal 25, that is, the 1-bit delay transmission line code, are added to the address input terminals A ₀ to _{A 7} of the storage element 21. Accordingly, summation logic conversion information and operand information corresponding to the input code are obtained at data output terminals D ₀ -D ₃ and D ₄ -D ₇ of the storage element 21.

Note that the transmission line code and operand code in Figure 4 are
Y ₁ ^m , b ₁ ^m , b ₂ ^m , Y ₂ ^m , b ₃ ^m , b ₄ ^m are the transmission input codes X ₁ ^m , a ₁ ^m , a ₂ m , X ₂ ^{m ,} a ₃ ^m , a ₄ ^m and 1-bit delayed operand sign Y ₁ ^m-1 , b ₁ ^m-1 , b ₂ ^m-1 , Y ₂ ^m-1 ,
After gray natural transformation of b ₁ ^m-1 and b ₂ ^m-1 , Y ₁ ^m = (X ₁ ^m + Y ₁ ^m-1 ) MOD4 and Y ₂ ^m = (X ₂ ^m
+Y ₂ ^m-1 ) The value obtained by calculating MOD4 is further subjected to natural gray conversion, and the transmission line code arrangement follows the logic conversion rule that results in a natural code arrangement. However, it is not necessary to perform gray-natural and natural-gray conversions.

Next, to explain the case where FIG. 3 is used as a reception logic circuit for 16QAM system, the storage element 21 stores the transmission line code of the natural type code constellation, the Gray type code constellation, or the rotationally symmetric code constellation as the original transmission input code. Differential logic conversion information for converting to a reception output code corresponding to the reception output code and operand information for the reception transmission line code are written to the input terminal 23, and the transmission line codes c ₁ ^m , c ₂ ^m , c ₃ ^m , c ₄ ^m is input, and the received output code a ₁ ^m , which has been subjected to differential logic conversion, is input to the output terminal 24.
A ₂ ^m , a ₃ ^m , and a ₄ ^m are obtained.

An example of a truth table according to the differential logic conversion rule in this circuit is shown in FIG. The transmission line codes are set in advance so that the address input codes A ₀ to A ₇ in the left column of FIG. 5 become the data output codes D ₀ to D ₇ in the right column.
c ₁ ^m , c ₂ ^m , c ₃ ^m , c ₄ ^m and the 1-bit delayed operand codes, that is, the transmission line codes c ₁ ^m-1 , c ₂ ^m-1 obtained 1 bit ahead of the transmission code. , c ₃ ^m-1 , c ₄ ^m-1 differential logic conversion information a ₁ ^m , for all input conditions of c 4 m-1 ,
Create a ₂ ^m , a ₃ ^m , a ₄ ^m and use them as the upper 4 bits of the data output, and transmit the transmission line codes c ₁ ^m , c ₂ ^m , c ₃ ^m ,
c ₄ ^m is stored in the storage element 21 as it is as the lower 4 bits of the data output. the result,
Transmission line code of input terminal 23 and 1-bit delay terminal 2
By applying the operand code obtained through 5, that is, the 1-bit delayed transmission line code, to the address input terminals A ₀ to _{A 7} of the storage element 21, the differential logic conversion information and the output code corresponding to the transmission line code are stored. Arithmetic information is available at data output terminals D ₀ -D ₃ and D ₄ -D ₇ of storage element 21. In addition, similar to Figure 4, the fifth
The received output symbols in the figure are X ₁ ^m , a ₁ ^m , a ₂ ^m , X ₂ ^m , a ₃ ^m ,
a ₄ ^m is the transmission line code Z _{1 m-1 obtained by preceding the transmission line codes Z 1} ^{m ,} c ₁ ^m , c ₂ ^m , Z ₂ ⁿ , c ₃ ^m , _{c 4} ^m by 1 bit,
After gray natural transformation of c ₁ ^m-1 , c ₂ ^m-1 , Z ₂ ^m-1 , c ₃ ^m-1 , c ₄ ^m-1 , X ₁ ⁿ = (Z ₁ ^m − Z ₁ ^m-1 ) MOD
4 and X ₂ ^m = (Z ₂ ^m - Z ₂ ^m-1 ) The value obtained by calculating MOD4 is further subjected to natural gray conversion. However, it is not necessary to perform gray-natural and natural-gray conversions.

Such a transmitting logic circuit that has written the summation logic conversion information and operand information in the storage element and a receiving logic circuit that has written the differential logic conversion information and operand information in the storage element are connected to the transmitting side of the same transmission path. and on the receiving side, and if no errors occur in the transmission path, that is, in the case of the 16QAM method,
If b ₁ ^m , b ₂ ^m , b ₃ ^m , b ₄ ^m and c ₁ ^m , c ₂ ^m , c ₃ ^m , c ₄ ^m are equal, a received output code matching the transmitted input code can be obtained.

FIG. 6 shows a general configuration of a ^2n- ary differential logic circuit to which the present invention is applied, and shows summation logic conversion information modulo ²ⁿ , operand information or differential logic conversion information modulo ²ⁿ , and A memory element 31 in which operand information is written and an n-series 1-bit delay terminal 32 are provided, and the input code from the ^2n- ary code input terminal 33 is input to addresses _A0 to _Ao-1 of the memory element 31. , the outputs D ₀ to _{D o-1} of the storage elements 31 are supplied to the 2 ⁿ -ary logic conversion code output element 34 . Memory element 31
The outputs D _o -D _2o-1 are supplied to address terminals A _o -A _2o-1 of the storage element 31 through a 1-bit delay element 32.

<Effects> As explained above, according to the present invention, the same code as the remaining data output is output to a part of the data output terminal of the memory element used in the differential logic circuit, or the same code as the input transmission line code is output. By outputting the code, a transmitting logic circuit or a receiving logic circuit can be realized. Therefore, a transmitting logic circuit or a receiving logic circuit can be realized with the same circuit configuration only by changing the storage element. Therefore, by using the present invention, manufacturing costs and design costs of differential logic circuits can be reduced.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a conventional 4PSK system differential logic circuit, Figure 2 is a diagram showing a 16QAM system differential logic circuit using a conventional memory element (ROM), and Figure 3 is a diagram showing a differential logic circuit using the present invention. FIG. 4 is a diagram showing an example of a truth table according to the summation logic conversion rule in this invention, and FIG. 5 is a diagram showing an example of a differential logic circuit in this invention. FIG. 6 is a diagram showing an example of a truth table according to the rule, and FIG. 6 is a diagram showing the general configuration of a differential logic circuit according to the present invention. 21, 31: Memory element, 23, 33: Code input terminal, 24, 34: Logic conversion code output terminal, 2
5,32:1 bit delay element.

Claims (1)

[Claims] 1 In a differential logic circuit that converts a 2 ^n- ary input code into a 2 ^n- ary transmission line code, or converts the transmission line code into a 2 ⁿ -ary output code corresponding to the original 2 ^n- ary input code, ² A memory element in which logical conversion information is written according to the logic conversion rule modulo n is provided, and a 2 ^n- ary input code or a 2 ^n- ary transmission line code is input to the address input terminal of the memory element, and the data output of the memory element is By adding a code obtained by delaying a part of the code obtained from the terminal by 1 bit, logic conversion information is obtained from the remaining data output terminal of the memory element, and the code of the data output terminal is returned to the address input terminal. is a differential logic circuit in which the memory element is configured to be the same as a 2n ^- ary transmission line code.