JPS58131851A - Differential logical circuit - Google Patents

Abstract

PURPOSE:To simplify the logical element of a logical circuit and to make the design of the circuit easy, by providing an element writing converting information setting 2<n> as a notation in advance to a logical operation part of a differential logical circuit and obtaining a 2<n>-notation output signal corresponding to a 2<n>-notation input code. CONSTITUTION:Transmission input codes a1-an from a transmission code input terminal 32 are written in a storage element 30 of a 2<n>-notation transmission logical circuit in advance as conversion information setting 2<n> as the natation, and the transmission input codes a1-an from the terminal 32 and a one-bit delay transmission line code from a one-bit delay element 31 are set as addresses and applied to the element 30. From an output terminal 33 of the element 30, transmission output codes b1-bn of incremental logical conversion information of 2<n>- notation corresponding to the codes a1-an are outputted. The 2<n>-notation reception logical circuit consists of a storage element 34 written with the conversion information in advance and a one-bit delay element 35, the input codes b1-bn from a tansmission line code input terminal 36 are converted, the codes a1-an are outputted to a reception code output terminal 27 to simplify the logical circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential logic circuit used in a communication system that transmits information using differential phase modulation such as digital phase modulation or amplitude phase modulation.

When transmitting a signal using digital phase modulation, since absolute phase cannot be transmitted, the signal is transmitted using information in the phase difference between carrier waves. This is called a differential logic method, and on the transmitting side, the phase corresponding to the information to be transmitted next is added to the phase of the carrier wave currently being transmitted, and the next phase is determined based on this result. On the other hand, the receiving side calculates the difference between the phase of the carrier wave currently being received and the phase of the carrier wave to be received next, and uses this result as output information.

These operations are performed using differential logic circuits to perform logical operations between digital information corresponding to the carrier wave phase, rather than directly calculating the sum or difference between the carrier wave phases. ing. The differential logic circuit with
A transmission logic conversion circuit for converting a 2n-ary input code into a 2n-ary transmission line code, and converting the transmitted transmission line code to the original 2n-ary transmission line code.
It is a general term for a reception logic conversion circuit for converting an n-ary input code into a 2n-ary output code corresponding to the n-ary input code.

Figure 1 shows a conventional differential logic circuit used in four-phase transmission differential modulation (4PSK), in which (a) is a transmission logic conversion circuit; (a) is a transmission logic conversion circuit;
b) shows a reception logic conversion circuit. That is, as shown in FIG. 1(a), the transmission logic conversion circuit converts two series of binary input code signals an, an and the transmission path code bjl, which is outputted 1 bit in advance by the 1-bit delay flip-flop 3.
4 between NOR circuit 1 and OR circuit 2 between
The phase of the carrier wave is changed based on this information, and the reception logic conversion circuit converts two series of binary transmission line codes as shown in FIG. 1(b). The NOR circuit 4 and the OR circuit 5 calculate the modulus of 4 between the transmission line code 5C+C and 2 obtained by 1 pilot n-1n-1 by the cr, c picture and the 1-bit delay flip-flop 6. It performs differential logic operations and outputs the results as information.

FIG. 2 is an overall configuration diagram of a transmitting/receiving device for the 16QAM system, in which (a) shows the transmitting side device and (b) shows the receiving side device. That is, the transmitting device sends four series of binary input codes 811,
812.821, 822, two sets of quaternary summation logic circuits 7, 8. 2-value to 4-value converters 9, 10 and 16QAM
modulator 1], and the receiving side device is 1.6 Q
A M demodulator 12 and two sets of discriminators 13, 1.4.
Consisting of 4 inverse difference logic circuits 1.5 and 1.6, the 16 QA and M transmission logic conversion circuits and reception logic conversion circuits are comprised of 1.5 and 1.6 quaternary summation logic circuits and quaternary difference logic circuits surrounded by broken lines. is an individual I using a gate element as in the case of Fig. 1.
It was realized by a combination of C parts.

In this way, conventional differential logic circuits are realized by combining individual IC components that use gate elements in the logic operation part, so as the number of multi-values increases, the number of gate elements used increases. However, the disadvantage was that the logic circuit configuration was complex and large-scale.

In order to solve the above-mentioned conventional drawbacks, the present invention provides a memory element in which conversion information is written in advance according to a logic conversion rule modulo 2n in a logic operation part of a differential logic circuit.
By obtaining a 2n-ary output code corresponding to an n-ary input code, thereby greatly simplifying the logic elements used in the differential logic circuit, and freely designing the logic conversion information to be written in the memory element, This is intended to provide flexibility in the design of transmission line code arrangement in digital phase modulation or amplitude phase modulation.

Figure 3 shows an embodiment of the differential logic circuit of the present invention, (a) shows a transmission logic conversion circuit for obtaining a 16QAM transmission line code, and (b) shows the same <16QAM transmission line code. 3 shows a reception logic conversion circuit for obtaining a reception output code.

First, the transmission logic conversion circuit shown in FIG. 3(a) will be explained. Addition is a storage element in which two series of quaternary summation logic conversion information is written, 2] is a 1-bit delay element, 22 is a transmission code A'7,
The input terminal of Aq is the input terminal, and B is the output terminal of the transmission line code Bn and BIN which have been subjected to summation logic conversion. An example of a truth table according to the summation logic conversion rule in this circuit system is shown in FIG. The transmission input code A'7,
Summation logic conversion information Bn, Bn for all input conditions of cod and 1-bit delay transmission line codes Bn-1, Bn-1 is created and stored in the storage element 20. As a result, the transmission input codes A'7, A'7 and 1 of the input terminal 22 are
1-bit delay transmission line code B-1 obtained by bit delay element 21. By adding Bn-1 to the address input terminal ao-27 of the memory (5) element 20, the summation logic conversion information corresponding to the code, that is, the transmission line code B? , B\ is obtained at output terminal B. In addition, the transmission line code B? in FIG. and Bq is the transmission input code A? , A-view and 1-bit delay transmission line code B+? -]
, After converting Bn-1 to alternating binary code, 13?
The values obtained by calculating -(A¥+[1?-1)・MOD4 and Bc(A¥+Bc1)・MOD4 are further converted into alternating binary codes.

Next, the reception logic conversion circuit shown in FIG. 3(b) will be explained.
24 is a storage element in which two series of differential logic conversion information modulo 4 is written; 5 is a 1-bit delay element; 26 is an input terminal for transmission line codes Cr and Cg; and 27 is a reception output code A that has been subjected to differential logic conversion. ';' is the output terminal of A view.

An example of a truth table according to the differential logic conversion rule in this circuit system is shown in FIG. In order that the manual code in the left column of FIG. 5 becomes the output code in the right column,
?・Receive input code C obtained 1 bit ahead of C'?
Logic conversion information A'7, A, and 9 for all input conditions of -1 and Cn-1 are created (6) and stored in the storage element 24. As a result, the received input code Cn, Cn of the input terminal 26 and the input code C? obtained 1 bit in advance by the 1-pit delay element 5 are obtained. -1,0n-1 to the address input terminal aO-27 of the memory element 24, the differential logic conversion information corresponding to the code, that is, the reception output code AV, A
ra is obtained at the output terminal 27. In addition, the received output code A? in FIG. and A view is the received input code C? .

Cn and 1-bit advance input code C? After converting -1 and C view-2 into natural binary code, A? -(C1;l
To? -1)・MOD4. , A¥=(Cε-Cyi-1)・
The value obtained by calculating MOD4 is converted into a natural binary code.

FIG. 6 is a general configuration diagram of a differential logic circuit to which the present invention is applied.
An n-ary reception logic conversion circuit is shown. By using such a transmission logic conversion circuit and a reception logic conversion circuit on the transmission side and reception side of the same transmission path, if no error occurs on the transmission path, a reception output code corresponding to the transmission input code can be obtained. It is possible (7). Further, the logical conversion information written in the memory elements 30 and 34 can be easily changed by changing the logical formula.

As explained below, according to the present invention, a differential logic circuit for obtaining a 2n output code corresponding to a 2n input code is provided with a logic corresponding to all input conditions according to the logic conversion rule modulo 2n. Since I received a memory element with conversion information written in it, a differential logic circuit can be realized with a simple circuit configuration, and by changing the logic conversion information written in the memory element, it is possible to create a differential logic circuit without changing the circuit configuration. The code arrangement of the digital transmission path can be easily changed without any trouble.

In particular, in differential logic circuits used in multilevel modulation systems such as 2nX2nQAM systems, as n increases, the circuit configuration becomes extremely complex and large-scale when using the conventional method of combining logic elements using individual ICs. However, if the circuit configuration of the present invention is used, a differential logic circuit can be easily constructed by simply increasing the capacity of the storage element and changing the logic conversion information (without significant changes to the circuit configuration). It is possible.

(8)

[Brief explanation of the drawing]

Figures 1 (a) and (+1) are diagrams showing conventional 4PSK differential logic circuits, and Figures 2 (a) and (b) are 16 Q A
Figure 3 (a) is an overall configuration diagram of the transmitting/receiving device for the M system.
), (b) is a diagram showing an example of a differential logic circuit for 16 Q A M using the present invention, and FIG. 4 is a diagram showing an example of a truth table according to the summation logic conversion rule (2). Figure 5 is a diagram showing an example of a truth table according to the differential logic conversion rule, and Figure 6 (a
) and (b) are general configuration diagrams of a differential logic circuit according to the present invention. 20, 24.30, 34... memory element, 2], ,
25, 31.35...1 bit delay element, 22.
32... Transmission code input terminal, 23.33... Transmission line code output terminal, 26.36... Transmission line code input terminal,
27, 37... Reception code output terminal. Agent Patent Attorney Makoto Suzuki (9) 27 Sae X Sae! 6 Rolling
Figure 3 Figure 4 Figure 6 Figure 5

Claims (1)

[Claims] (J.
In a differential logic circuit that converts to an n-ary output code,
It is equipped with a memory element in which logic conversion information is written in advance according to the logic conversion rule modulo 2n, and stores the 2n-ary input code and the 2n-ary transmission line code outputted 1 bit ahead of the code, or the 2n-ary transmission line code and the corresponding code. A differential logic circuit characterized in that a transmission line code obtained one bit ahead of the code is added to the address input terminal of the storage element, and logic conversion information is obtained from the output data terminal.