JP3134746B2 - Digital wireless communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device using a quaternary digital modulation / demodulation system, and more particularly to a communication device using a quaternary digital modulation / demodulation system for monitoring line quality using parity bits.

[0002]

2. Description of the Related Art As a four-level digital modulation / demodulation system, there are four types of digital modulation / demodulation systems.
A phase-phase modulation / demodulation (4PSK) method is widely used.
In this modulation and demodulation method, there is a possibility that uncertainty may occur in transmission data due to phase inversion of a reproduced carrier wave in a receiver, and differential logic conversion is used to remove the uncertainty. In addition, a normal digital communication apparatus uses a parity monitoring method in which an even or odd parity bit is inserted into a part of a transmission signal for monitoring the line quality. FIG. 2 is a block diagram showing a communication device using a conventional four-phase modulation / demodulation method.

In this communication apparatus, when a digital signal whose data bits periodically include a predetermined parity bit is input to an input terminal 100, the digital signal is converted from one column to two columns for input to a quadrature modulator 22. Is performed by the one-row / two-row conversion circuit 20, and the two-row signals a and b are subjected to differential logic conversion (sum operation) by the differential logic conversion circuit 21. The signal subjected to the differential logic conversion is modulated by the quadrature modulator 22 and then sent to the transmission path 24 by the transmitter 23. The transmission signal sent to the transmission path 24 is received by the receiver 25 on the receiving side, and the received signal is demodulated by the demodulator 26 and sent to the differential logic reverse conversion circuit 27.

In the differential logic reverse conversion circuit 27, a demodulator 26
After performing the differential reverse logic conversion (difference calculation) of the two columns of digital signals output from the, the two-column / one-column conversion circuit 28 performs two-column / one-column conversion and outputs the result to the output terminal 200.

In the above-mentioned system using the differential logic conversion, a gray code is usually used, and if one error occurs in a transmission line, two errors occur in response to the error, so that parity monitoring cannot be performed. was there.

[0006] To solve this drawback, a technique has been disclosed in, for example, Japanese Patent Publication No. 3-70420, in which parity monitoring can be performed by appropriately selecting the Hamming distance between words, for example. Since the technique is not applied to the four-phase modulation and demodulation but is applied to the multi-level modulation and demodulation of eight or more values, it cannot be applied to the four-phase modulation and demodulation.

[0007]

Table 1 is a table showing the word arrangement by the Gray code, and is selected so that the Hamming distance between words corresponding to adjacent signals is always 1. .

FIG. 3 shows a signal arrangement S0 of the four-phase modulation / demodulation system.
To S3. Note that S0 to S3 indicate signals of each word in Table 1 above.

In such a quaternary digital radio communication apparatus, a transmission path error has a high possibility that a transmitted code is erroneous to a code having an adjacent phase (for example, S0 ← → S1). And a number of errors corresponding to the Hamming distance between the two. That is, a 1-bit error in the transmission path is such that a Gray code in which the Hamming distance between adjacent words in S0 to S3 is always 1 causes an error of a Hamming distance of 1 in each of the two codes in which the error occurs, Since a bit error in two codes is a two-bit error, there is a problem that a two-bit continuous code error is generated by differential logical conversion.

As a result, in the Gray code, one transmission line error generates an even number of bit errors, so that there is a problem that parity monitoring cannot be applied in the conventional technique.

[0011]

[MEANS FOR SOLVING THE PROBLEMS]
The line communication device adds a predetermined parity bit to the data bit.
periodAt TDigital signal insertedColumnTo2 columns per bit
, And only one signal sequence is 2NT (N is natural
Means for generating two first signal sequences delayed by (number)
And the delayed signal sequence of the first signal sequence
Is converted to two signal trains, and only one of the signal trains is delayed by NT.
Means for generating an extended second sequence of second signals;
The non-delayed signal sequence of the signal sequence of
Signal sequence, and only one signal sequence is delayed by NT
Means for generating a third signal sequence of the second and third signals,
Are converted into a single signal sequence, and each signal sequence is
Means for differential logic conversion and transmission by four-phase modulationWhen, Said
After demodulating the transmitted signal, reverse-differential logic conversion is performed.
The same delay is given to the signal sequence different from
Has means to output as a signal sequenceCharacterized by

Further, the digital radio communication apparatus of the present invention converts a digital signal, in which predetermined parity bits are periodically inserted into data bits, into two columns and performs a differential logic conversion using a four-phase phase modulation / demodulation system. In a transmitting digital wireless communication apparatus, the transmitting side converts one input signal into one signal.
A first one-row / two-row conversion circuit for converting two rows for each unit ,
Connected to one of the outputs of the first one-column / two-column conversion circuit, and 2 × N times (N
Is a positive integer), and outputs the output of the first delay circuit and the output of the other first one-column / two-column conversion circuit in two columns for each bit. And one of the outputs of the second and third one-column / two-column conversion circuits, and connected to one of the columns of the second and third one-column / two-column conversion circuits. second inputs and third delay circuits, the outputs of said second first column / two columns conversion circuit of the second delay circuit having N times the delay time, 1
Enter the first two columns / one row converting circuit for converting the one line for each bit, and an output of said third output and said third first column / two columns conversion circuit of the delay circuit, each bit a second two columns / one row converting circuit for converting the 1 row, the first, inputs the output of the second two columns / one row converting circuit, and the differential logic conversion circuit for differential conversion, the A quadrature modulator that performs quadrature modulation on the output of the differential logic conversion circuit, and a transmitter that transmits the output of the quadrature modulator, on the receiving side, a receiver that receives a transmission signal from the transmitter, A demodulator that receives the output of the receiver and demodulates two columns of signals, a differential inverse logic conversion circuit that performs differential inverse conversion of the output of the demodulator, and an output of the differential inverse logic conversion circuit. A fourth / fifth one-column / two-column conversion circuit for converting each bit into two columns,
Fourth and fifth delays having a delay time N times the parity bit period inserted in columns other than the column into which the second and third delay circuits are inserted, of the output of the column / two-column conversion circuit Circuit, the output of the fourth delay circuit and the output of the fourth one-column / two-column conversion circuit, and converting the output to one column for each bit .
, A second column / single column conversion circuit, an output of the fifth delay circuit, and an output of the fifth single column / two column conversion circuit, and a fourth two column / 1 conversion unit for converting one bit into one column. A column conversion circuit, and the first and second columns / outputs of the two / one column conversion circuit.
A sixth delay circuit having a delay time of 2N times the parity bit period inserted in a column other than the column in which the delay circuit is inserted, and an output of the sixth delay circuit and another two columns / one column And a fifth two-column / one-column conversion circuit which receives the output of the conversion circuit, converts the data into one column for each bit, and outputs the converted data.

By providing the above means, the time relationship between a and b of the configuration S (a, b) of each word transmitted in the same parity cycle is shifted by at least one parity cycle, so that the continuity generated in the transmission path is The even number of errors can be distributed to the odd number at the output point of the delay circuit on the receiving side, so that parity monitoring becomes possible, and the above problem can be solved.

[0014]

FIG. 1 is a block diagram showing a configuration of a communication apparatus using a four-phase modulation / demodulation system according to an embodiment of the present invention.

According to the present invention, when a digital signal including a data bit and a parity bit is input, a one-to-two column conversion is performed by a one-to-two column conversion circuit 2 for input to a quadrature modulator.
Performed by 0. 2 of the output of the one-column / two-column conversion circuit 20
Among the columns, for example, a delay circuit 2 equivalent to twice the parity period is connected to column a. Therefore, the output columns a and b are given a time difference of two parity periods.

Next, each of the columns a and b is further converted into two columns through one-column / two-column conversion circuits 3 and 4, and the column a is converted to a1, a
The column b is converted into the columns b1 and b2 into two columns.

Further, delay circuits 5 and 6 corresponding to the parity period are connected to the columns a1 and b1. Therefore, the output of the columns a1 and b1 is given a further time difference of one parity cycle as compared with the columns a2 and b2.

Next, the column a1 and column a2, and the column b1 and column b2 are subjected to 2-column / 1-column conversions 7 and 8, and the two signals aD and b
Convert to column D. Therefore, at the next input point of the differential logic conversion circuit 9, the aD column and bD column have two parity periods, aD column, b
Even in each of the D columns, a time difference of one parity cycle is given every other bit.

That is, a and b constituting the word transmitted to the transmission line are paired with a shift of two parity periods.

Next, the differential logic conversion circuit 21 performs differential logic conversion (sum operation) on the input signal. The signal subjected to the differential logic conversion is modulated by the quadrature modulator 22 and then sent to the transmission path 24 by the transmitter 23. The transmission signal sent to the transmission path 24 is received by a receiver 25 on the receiving side, and the received signal is demodulated by a demodulator 26.

Thereafter, the demodulated signal is subjected to differential inverse logic conversion (differential operation) of two columns of digital signals aD and bD output from the demodulator 26 by a differential logic inverse converter 27.
Is performed, each of the aD column and the bD column is further divided by one line / 2.
The column conversion is performed by the one-column / two-column conversion circuits 9 and 10 to convert the aD column into the aD1 column, the aD2 column into the bD column, and the bD1 column into the bD2 column.

Next, delay circuits 11 and 12 corresponding to the parity period are connected to the columns aD2 and bD2. As a result, the output aD2 and bD2 columns have the same time relationship as the aD1 and bD1 columns. Next, a two-column / one-column conversion circuit 101, 1
02, the aD1 column and aD2 column become the ad column, the bD1 column,
The bD2 column is converted to a bd column. Since the ad column and the bd column have a time difference of two parity periods on the transmission side, a delay circuit 15 equivalent to twice the parity period is connected to the bd column this time. The output has the same time relationship.

By connecting the two-row / one-row conversion circuit 28 to the output, the transmitted signal is correctly output as a signal appearing as an output signal.

Next, a description will be given of how an even number of errors in a transmission line are dispersed to an odd number and parity monitoring can be performed according to the present invention.

First, a description will be given with reference to FIG. There are the following four paths in which an error occurs in the transmission path. (← →
(1) S0 ← → S1, ie, (a, b) = (0,0) ← → (0,1) (2) S1 ← → S2, ie, (a, b) = (0,1) ← → (1,1) (3) S2 ← → S3, ie, (a, b) = (1,1) ← → (1,0) (4) S3 ← → S0, ie, (a , B) = (1, 0) ← → (0, 0) In the case of (1), the column b of (a, b) is erroneously changed to 0 ← → 1. In the case of 0 → 1, when the differential logic reverse conversion, that is, the difference operation (subtraction of the quaternary number with the previous word) is performed on the receiving side, the operation is performed according to the state of the previous word, that is, 0, 1, 2, 3 of the quaternary number. The result is the quaternion 1, 0, 3, 2. Normal reception (0 →
0), the result of the operation is quaternary 0, 3, 2,
Therefore, when this is compared with the binary word (a, b), (0,0) → (0,1), (1,0) → (0,0), (1,1) → ( (1,0), (0,1) → (1,1), and it can be seen that the errors are spread to the b column in the first and third columns and to the a column in the second and fourth columns. Here, as a result of the occurrence of an error in the column b, the probability that the error propagates to the column a of the next word and the probability that the error propagates to the same column b is １ ／.

Similarly, for (2), (3), and (4), the probability that an error occurring in column a or column b of the previous word propagates to column a or column b of the next word is 1/2. It is.

Therefore, in the four-phase modulation / demodulation system using the Gray code, the probability that an error in the transmission path spreads to the same column of words is １ ／. The probability of spreading to different columns is also 1 /
2.

In the case of spreading to the same column, the bits in the column are shifted by one parity period every other bit on the transmission path, so that when the time difference is restored on the receiving side, an odd number of errors occur every two periods. Parity monitoring is possible because of the distribution.

In the case of spreading to a different column, the error is dispersed in the signal at a time two parity periods apart due to the effect of the delay circuit for two parity periods, and this is different from the case of spreading to the same column. , 100% parity monitoring becomes possible.

Here, it is assumed that the delay circuits 2 and 15 are delayed by twice the parity period and the delay circuits 5, 6, 11 and 12 are delayed by the parity period. The above effect is also obtained when the delay time is N times (N is a positive integer).

In the embodiment described above, the delay circuits 2, 5, 6 on the transmission side and the delay circuits 11, 1 on the reception side.
The use of 2 and 15 enables monitoring of 100% parity. However, when the configuration in which the delay circuits 2 and 15 are deleted and connected as they are is used, the monitoring probability is reduced to 1/2. Practical monitoring is possible.

[0032]

As described above in detail, according to the present invention, even in a communication apparatus to which a quaternary phase modulation / demodulation system using a gray code is applied, even a transmission line error with a 100% probability is obtained. Can be spread to an odd number, so that there is an effect that the line quality can be monitored by the parity bit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a communication device using a conventional four-phase modulation / demodulation system.

FIG. 3 is a diagram showing a signal arrangement of a four-phase modulation / demodulation system.

FIG. 4 is a word arrangement based on a Gray code.

[Explanation of symbols]

 2, 5, 6, 11, 12, 15 delay circuit 3, 4, 9, 10, 20 one-column / two-column conversion circuit 7, 8, 13, 14, 28 two-column / one-column conversion circuit 21 differential logic conversion Circuit 22 Quadrature modulator 23 Transmitter 24 Transmission line 25 Receiver 26 Demodulator 27 Differential logic reverse conversion circuit 100 Input data 200 Output data

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 27/18

Claims (4)

(57) [Claims] 1. A method according to claim 1, wherein a predetermined parity bit is applied to the data bit.
PeriodAt TDigital signal insertedColumnTo2 columns of 1 bit
Is converted to a signal sequence, and only one signal sequence is 2NT (N is natural
Means for generating two first signal sequences delayed by (number)
When, The delayed signal sequence of the first signal sequence is divided by 2 for each bit.
Is converted into a signal sequence, and only one signal sequence is delayed by NT.
Means for generating two second signal sequences, The undelayed signal sequence of the first signal sequence is bit by bit
Convert to two signal trains, delay only one signal train by NT
Means for generating two sets of third signal sequences, and the second and third signal sequences.
And the third signal sequence are converted into one signal sequence, respectively.
Means for differentially logically converting a signal sequence and transmitting it by four-phase modulation
 When, After demodulating the transmitted signal, perform a differential logic reverse conversion, and
The same delay is given to the signal sequence that is different from the
There is a means to output as a signal sequence Characterized by
Digital wireless communication device. 2. A digital radio communication apparatus for performing radio transmission using a four-phase phase modulation / demodulation method for converting a digital signal in which predetermined parity bits are periodically inserted into data bits into two columns and performing differential logic conversion. Side, the input signal is converted into two columns for each bit, the first one column / 2
A column conversion circuit, connected to one of the columns of the output of the first one-column / two-column conversion circuit, and 2 × N times (N × N) of the period of the parity bit.
Is a positive integer), and the output of the first delay circuit and the output of the other first one-column / two-column conversion circuit are each two columns per bit. A second / third one-column / two-column conversion circuit, which is connected to either one of the outputs of the second and third one-column / two-column conversion circuits, and Second and third delay circuits having an N-times delay time, an output of the second delay circuit and an output of the second one-column / two-column conversion circuit, and one column for each bit A first two-column / one-column conversion circuit, and an output of the third delay circuit and an output of the third one-column / two-column conversion circuit, which are converted into one column for each bit. A second two-column / one-column conversion circuit, and an output of the first and second two-column / one-column conversion circuit,
A differential logic conversion circuit that performs differential conversion, a quadrature modulator that quadrature modulates an output of the differential logic conversion circuit, and a transmitter that transmits an output of the quadrature modulator; A receiver that receives a transmission signal from the receiver, a demodulator that receives an output of the receiver and demodulates two columns of signals, and a differential reverse logic conversion circuit that performs differential reverse conversion on the output of the demodulator. the output of the differential inverse logic conversion circuit inputs respectively, 1 bi
A fourth / fifth one-column / two-column conversion circuit that converts the data into two columns for each unit, and the second and third ones of the outputs of the fourth and fifth one-column / two-column conversion circuits Fourth and fifth delay circuits having a delay time N times the parity bit period inserted in columns other than the column in which the delay circuit is inserted; the fourth delay circuit and the fourth one column / 2 A third two-column / one-column converter that receives an output of the column converter and converts the output into one column for each bit ; an output of the fifth delay circuit and an output of the fifth one-column / two-column converter And a fourth two-column / one-column conversion circuit that converts one bit into one column, and the first delay circuit among the outputs of the third and fourth two-column / one-column conversion circuits A sixth delay circuit having a delay time of 2N times the parity bit period inserted in a column other than the column in which is inserted, and an output of the sixth delay circuit and another A digital radio communication apparatus, comprising: a fifth two-column / one-column conversion circuit which receives an output of a two-column / one-column conversion circuit, converts the data into one column for each bit, and outputs the converted data. 3. The digital radio communication apparatus according to claim 1, wherein said digital signal uses a Gray code. (4)Predetermined parity bits for data bits
2 digital signal sequences inserted at a period T per bit
Means for converting the signal sequence into two signal sequences and generating two first signal sequences
When, The first signal sequence is converted into two signal sequences for each bit.
And delays only one signal train by NT (N is a positive integer)
Means for generating two second signal sequences, The other of the first signal sequence is converted into two signal sequences for each bit.
The third row of the second row is converted and only one signal row is delayed by NT.
Means for generating a signal sequence of The second and third signal trains are each converted into one signal train.
, And perform differential logic conversion on each signal sequence and send them by four-phase modulation.
Means of trust When, After demodulating the transmitted signal, perform a differential logic reverse conversion, and
The same delay is given to the signal sequence that is different from the
There is a means to output as a signal sequence Characterized by
Digital wireless communication device.