JPH09162941A - Digital radio communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a parity cannot be monitored since two errors occur when one error occurs in a transmission line at the time of using a gray code. SOLUTION: A transmission-side connects a one string/two strings conversion circuit 20 with a delay circuit 2 whose period for inserting a parity bit into one string in the outputs is 2N-times. The other one string/two strings conversion circuits 3 and 4 are connected to the string to which the delay circuit is connected and the string to which it is not connected. Delay circuits 5 and 6 whose periods for inserting the parity bit are connected to one string in the outputs of the two strings. The string where the bits of the respective strings are arranged so that the signals deviated by one period are inserted into an orthogonal modulator 22 through a differential logic conversion circuit 21. A reception-side connects delay circuits 11 and 12 to the signal string opposite to the transmission side in the two strings, and a delay circuit 15 to the string opposite to the transmission side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device using a 4-value digital modulation / demodulation system, and more particularly to a communication device using a 4-value digital modulation / demodulation system for monitoring line quality by parity bits.

[0002]

2. Description of the Related Art As a four-value digital modulation / demodulation system, there are four
The phase modulation / demodulation (4PSK) method is widely used.
In this modulation / demodulation system, there is a possibility that transmission data may have indeterminacy due to phase inversion of the reproduced carrier wave in the receiver, and differential logic conversion is used to remove it. In addition, a normal digital communication apparatus uses a parity monitoring method in which even or odd parity bits are inserted in a part of a transmission signal for line quality monitoring. FIG. 2 is a block diagram showing a communication device using a conventional 4-phase phase modulation / demodulation method.

In this communication device, when a digital signal which periodically includes a predetermined parity bit in data bits is input to the input terminal 100, conversion from one column to two columns is performed for input to the quadrature modulator 22. Is performed in the 1-column / 2-column conversion circuit 20, and the signals a and b in the 2-column are subjected to differential logic conversion (sum calculation) in the differential logic conversion circuit 21. The signal subjected to the differential logic conversion is modulated by the quadrature modulator 22 and then sent to the transmission line 24 by the transmitter 23. The transmission signal sent to the transmission path 24 is received by the receiver 25 on the receiving side, the received signal is demodulated by the demodulator 26 and sent to the differential logic inverse conversion circuit 27.

In the differential logic inverse conversion circuit 27, the demodulator 26
After performing the differential inverse logic conversion (difference operation) of the digital signals of the two columns output from, the two-column / one-column conversion circuit 28 performs the two-column / one-column conversion and outputs it to the output terminal 200.

In the method using the differential logic conversion described above, the Gray code is usually used, and when one error occurs in the transmission line, two errors occur correspondingly, so that the parity cannot be monitored. was there.

In order to solve this drawback, a technique capable of performing parity monitoring by appropriately selecting the Hamming distance between words is described in, for example, Japanese Patent Publication No. 3-70420. It is not related to 4-phase phase modulation / demodulation, but is a technique applied to a multi-level modulation / demodulation system with eight or more values, and cannot be applied to a 4-phase phase modulation / demodulation system.

[0007]

Table 1 is a table showing a word arrangement according to the Gray code, and is selected so that the Hamming distance between words corresponding to signals adjacent to each other is always 1. .

FIG. 3 shows a signal arrangement S0 of the 4-phase phase modulation / demodulation system.
~ S3 is shown. It should be noted that S0 to S3 indicate signals of each word in Table 1 above.

In such a four-valued digital wireless communication apparatus, there is a high possibility that a transmission path error will cause a transmitted code to be mistaken for a code in an adjacent phase (for example, S0 ← → S1). Therefore, the number of errors corresponding to the Hamming distance between and will occur. That is, for a 1-bit error in the transmission path, a Gray code in which the Hamming distance between adjacent words in S0 to S3 is always 1 causes an error of a Hamming distance of 1 in each of the two error code, Since a bit error in two codes becomes a 2-bit error, there is a problem that a 2-bit continuous code error is generated by the differential logic conversion.

As a result, in the Gray code, since one transmission path error causes an even number of bit errors, there is a problem that the conventional technology cannot apply the parity monitoring.

[0011]

A digital radio communication apparatus of the present invention is a four-phase phase modulation / demodulation system for converting a digital signal in which a predetermined parity bit is periodically inserted into a data bit into two columns and performing differential logic conversion. In a digital wireless communication device for wirelessly transmitting using the above-mentioned, the word structure of the two columns of the digital signal is transmitted with a shift of at least one parity period.

Furthermore, the digital radio communication apparatus of the present invention uses a four-phase phase modulation / demodulation system for converting a digital signal in which a predetermined parity bit is periodically inserted into a data bit into two columns and performing differential logic conversion. In a digital wireless communication device for transmission, on the transmission side, one of a first 1-column / 2-column conversion circuit for converting an input signal into two columns and an output of the first 1-column / 2-column conversion circuit is provided. A first delay circuit connected to a column and having a delay time of 2 × N times the period of the parity bit (N is a positive integer); an output of the first delay circuit and the other first circuit. Either the second or third 1-column / 2-column conversion circuit for converting the output of the column / 2-column conversion circuit into two columns or the output of the second / third 1-column / 2-column conversion circuit Delay time of N times the period of the parity bit connected to one column The second and third delay circuits having the above, the output of the second delay circuit and the output of the second one-column / two-column conversion circuit are input, and the first two-column / 1 is converted. A column conversion circuit, an output of the third delay circuit and the third 1
A second two-column / one-column conversion circuit that receives the output of the column / two-column conversion circuit and converts it into one column, and the first and second two-column / 1
A differential logic conversion circuit that inputs the output of the column conversion circuit and performs differential conversion, a quadrature modulator that quadrature modulates the output of the differential logic conversion circuit, and a transmitter that transmits the output of the quadrature modulator are provided. The receiving side has a receiver for receiving a transmission signal from the transmitter, a demodulator for receiving the output of the receiver and demodulating signals in two columns, and a differential inverse conversion for the output of the demodulator. Differential inverse logic conversion circuit and a fourth and fifth 1-column / column for converting the outputs of the differential inverse-logic conversion circuit into two columns, respectively.
Of the outputs of the two-column conversion circuit and the fourth and fifth one-column / two-column conversion circuits, the parity bit cycle of the parity bit cycle inserted in a column other than the column in which the second and third delay circuits are inserted. Fourth and fifth delay circuits having a delay time of N times, a third second circuit for inputting outputs of the fourth delay circuit and the fourth first-column / second-column conversion circuit, and converting into a single column A column / one-column conversion circuit, a fourth two-column / one-column conversion circuit which receives the outputs of the fifth delay circuit and the fifth one-column / two-column conversion circuit, and converts the output into one column, A sixth having a delay time of 2N times the parity bit period inserted in a column other than the column in which the first delay circuit is inserted among the outputs of the third and fourth 2-column / 1-column conversion circuits. 5th column for inputting the output of the sixth delay circuit and the output of the other 2-column / 1-column converting circuit, and converting and outputting to 1 column And a single row converting circuit.

By providing the above means, the time relationship between a and b of the composition S (a, b) of each word transmitted in the same parity cycle is shifted by at least one parity cycle, so that the continuity generated in the transmission path is increased. It is possible to disperse an even number of errors to an odd number at the output point of the delay circuit on the receiving side, and therefore, it becomes possible to monitor the parity and solve the above problem.

[0014]

1 is a block diagram showing the configuration of a communication device using a 4-phase phase modulation / demodulation system according to an embodiment of the present invention.

According to the present invention, when a digital signal containing data bits and parity bits is input, the 1-column / 2-column conversion is performed by the 1-column / 2-column conversion circuit 2 for input to the quadrature modulator.
Performed by 0. 2 of the output of the 1-column / 2-column conversion circuit 20
Of the columns, for example, the delay circuit 2 corresponding to twice the parity period is connected to the column a side. Therefore, the a and b columns of the output are given a time difference of two parity periods.

Next, each of the columns a and b is further converted into two columns through the one-column / two-column conversion circuits 3 and 4, and the column a is a1, a.
2 columns and b column are converted into b1 and b2 columns.

Further, delay circuits 5 and 6 corresponding to the parity period are connected to the columns a1 and b1, respectively. Therefore, the a1 and b1 columns of the output are given a time difference of one parity cycle more than the a2 and b2 columns.

Next, the a1 column and the a2 column, and the b1 column and the b2 column are subjected to the 2 column / 1 column conversion 7 and 8, and again the 2 columns of the signals aD column and b.
Convert to column D. Therefore, at the next input point of the differential logic conversion circuit 9, the aD column and the bD column have two parity periods, the aD column and the b column.
Within each column of D columns, a time difference of one parity cycle is given every other bit.

That is, a and b which compose the word transmitted to the transmission line are a pair of two parity cycles shifted.

Next, the differential logic conversion circuit 21 performs differential logic conversion (sum calculation) on the input signal. The signal subjected to the differential logic conversion is modulated by the quadrature modulator 22 and then sent to the transmission line 24 by the transmitter 23. The transmission signal sent to the transmission path 24 is received by the receiver 25 on the receiving side, and the received signal is demodulated by the demodulator 26.

The demodulated signal is then subjected to differential inverse logic conversion (difference operation) of the two digital signals aD and bD output from the demodulator 26 by the differential logic inverse conversion circuit 27.
After performing the above, the aD row and the bD row are each further 1 row / 2.
Column conversion is performed by the 1-column / 2-column conversion circuits 9 and 10 to convert aD columns into aD1 columns, aD2 columns and bD columns into bD1 columns and bD2 columns.

Next, the delay circuits 11 and 12 corresponding to the parity period are connected to the aD2 column and the bD2 column. As a result, the outputs aD2 and bD2 have the same time relationship as the aD1 and bD1. Next, the 2-column / 1-column conversion circuit 101, 1
02, aD1 column, aD2 column to ad column, bD1 column,
Convert bD2 column to bd column. Since there is a time difference of two parity cycles on the transmitting side between the ad sequence and the bd sequence, the delay circuit 15 corresponding to twice the parity period is connected to the bd sequence this time. The outputs have the same time relationship.

By connecting the 2-column / 1-column conversion circuit 28 to the output, the transmitted signal is correctly output as the signal appearing as the output signal.

Next, it will be explained that according to the present invention, an even number of errors on the transmission line are dispersed into an odd number and parity monitoring can be performed.

First, FIG. 3 will be described again. There are the following four paths in which errors occur in the transmission path. (← →
(1) S0 ← → S1, ie (a, b) = (0,0) ← → (0,1) (2) S1 ← → S2, ie (a, b) = (0,1) ← → (1,1) (3) S2 ← → S3, that is, (a, b) = (1,1) ← → (1,0) (4) S3 ← → S0, that is (a , B) = (1,0) ← → (0,0) (1), the column b in (a, b) is erroneous as 0 ← → 1. In the case of 0 → 1, when differential logical inverse conversion, that is, difference calculation (subtraction of a quaternary number from the previous word) is performed on the receiving side, the state of the previous word, that is, quaternary numbers 0, 1, 2, 3 The result is the quaternary numbers 1, 0, 3, 2. Received normally (0 →
0), the result of the operation is the quaternary number 0, 3, 2,
Therefore, when this is compared with the binary word (a, b), it is (0,0) → (0,1), (1,0) → (0,0), (1,1) → ( 1,0), (0,1) → (1,1), and it can be seen that the error spreads to the b column in the first and third columns and to the a column in the second and fourth columns. Here, it is shown that, as a result of the occurrence of an error in the column b, the probability that the error propagates to the column a of the next word and the probability that it propagates to the same column b are 1/2.

Similarly, with respect to (2), (3), and (4), the probability that an error occurred in the a or b column of the previous word will propagate to the a or b column of the next word is 1/2. Is.

Therefore, in the four-phase phase modulation / demodulation system using the Gray code, the probability that an error in the transmission line will spread to the same column of words is 1/2. Also, the probability of spreading to different columns is 1 /
2.

When the error spreads to the same column, the bits in the column are shifted by one parity cycle every other bit on the transmission path. Therefore, when the time difference is restored on the receiving side, an error occurs every two cycles. Since it is distributed, the parity can be monitored.

Further, when it spreads to different columns, the error is dispersed in the signal of the time two parity cycles apart due to the effect of the delay circuit for two parity cycles, and this is different from the case where it spreads to the same column. Therefore, 100% parity monitoring is possible.

Here, the delay circuits 2 and 15 delay twice the parity cycle, and the delay circuits 5, 6, 11 and 12 delay by the parity cycle, but in general, they are 2N times the parity cycle and the parity cycle, respectively. Even when the delay time is N times (N is a positive integer), the above effect is achieved.

In the embodiment described above, the delay circuits 2, 5 and 6 are provided on the transmitting side and the delay circuits 11 and 1 are provided on the receiving side.
Although it is possible to monitor the parity of 100% by using 2 and 15, the monitoring probability is reduced to 1/2 when the delay circuits 2 and 15 are deleted and the configuration is connected as it is. Practical monitoring is possible.

[0032]

As described above in detail, according to the present invention, even in a communication device to which a four-level phase modulation / demodulation method using Gray code is applied, there is an even number of transmission line errors with 100% probability. Can be spread to an odd number, so that the line quality can be monitored by the parity bit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a communication device using a conventional 4-phase phase modulation / demodulation method.

FIG. 3 is a diagram showing a signal arrangement of a 4-phase phase modulation / demodulation method.

FIG. 4 is a word arrangement using a Gray code.

[Explanation of symbols]

 2, 5, 6, 11, 12, 15 Delay circuit 3, 4, 9, 10, 20 1 column / 2 column conversion circuit 7, 8, 13, 14, 28 2 column / 1 column conversion circuit 21 Differential logic conversion Circuit 22 Quadrature modulator 23 Transmitter 24 Transmission line 25 Receiver 26 Demodulator 27 Differential logic inversion circuit 100 Input data 200 Output data

Claims (4)

[Claims] 1. A digital wireless communication apparatus for wirelessly transmitting a digital signal, in which a predetermined parity bit is periodically inserted into a data bit, into two columns and performing differential logic conversion using a four-phase phase modulation / demodulation method. At least one word arrangement of two columns of digital signal
A digital wireless communication device, wherein transmission is performed by shifting the parity cycle. 2. A digital wireless communication device for wirelessly transmitting a digital signal, in which a predetermined parity bit is periodically inserted into a data bit, is converted into two columns and differentially logically converted using a four-phase phase modulation / demodulation method. On the side, the first 1-column / 2-column conversion circuit for converting the input signal into two columns and the output of the first 1-column / 2-column conversion circuit are connected to either column, and the parity bit of the parity bit is connected. 2 × N times the cycle (N
Is a positive integer), and a first delay circuit for converting the output of the first delay circuit and the output of the other first first-column / second-column conversion circuit into two columns, respectively. 2nd and 3rd
And a column having a delay time N times the cycle of the parity bit, the column being connected to either one of the outputs of the first-column / two-column converting circuit and the second and third first-column / 2-column converting circuits. 2nd and 3rd delay circuits, 1st 2nd column / 1 which inputs the output of the 2nd delay circuit and the output of the 2nd 1st column / 2nd column conversion circuit
A column conversion circuit, and a second two columns / 1 for converting the output of the third delay circuit and the output of the third one-column / two-column conversion circuit into one column.
A column conversion circuit, and inputs of outputs of the first and second two-column / one-column conversion circuits,
A differential logic conversion circuit for performing differential conversion; a quadrature modulator for quadrature modulating the output of the differential logic conversion circuit; and a transmitter for transmitting the output of the quadrature modulator. A receiver for receiving a transmission signal from a receiver, a demodulator for receiving the output of the receiver and demodulating signals in two columns, and a differential inverse logic conversion circuit for performing differential inverse conversion on the output of the demodulator, Outputs of the fourth and fifth one-column / two-column conversion circuits, each of which receives the output of the differential inverse logic conversion circuit and converts it into two columns. Of these, fourth and fifth delay circuits having a delay time N times as long as the parity bit period inserted into columns other than the column into which the second and third delay circuits are inserted; and the fourth delay. Circuit and the output of the fourth 1-column / 2-column conversion circuit is input and converted into a 1-column third 2-column / 1-column converter A circuit; a fourth two-column / one-column conversion circuit which receives the outputs of the fifth delay circuit and the fifth one-column / two-column conversion circuit and converts the output into one column; A second delay circuit having a delay time of 2N times the parity bit period inserted in a column other than the column in which the first delay circuit is inserted among the outputs of the 2-column / 1-column conversion circuit of Fifth two columns / inputting the output of the sixth delay circuit and the output of the other two-column / one-column converting circuit, converting the output into one column / outputting
A digital wireless communication device comprising a one-column conversion circuit. 3. The digital wireless communication device according to claim 1, wherein the digital signal uses a Gray code. 4. The digital wireless communication device according to claim 2, wherein, in the digital wireless communication device, the first delay circuit and the sixth delay circuit are deleted and the connection is made without delay. apparatus.