JPS62133842A - Multi-value orthogonal amplitude modulation system - Google Patents

Multi-value orthogonal amplitude modulation system

Info

Publication number
JPS62133842A
JPS62133842A JP60274003A JP27400385A JPS62133842A JP S62133842 A JPS62133842 A JP S62133842A JP 60274003 A JP60274003 A JP 60274003A JP 27400385 A JP27400385 A JP 27400385A JP S62133842 A JPS62133842 A JP S62133842A
Authority
JP
Japan
Prior art keywords
converter
signal point
signal
differential
amplitude modulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60274003A
Other languages
Japanese (ja)
Inventor
Noboru Iizuka
昇 飯塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60274003A priority Critical patent/JPS62133842A/en
Publication of JPS62133842A publication Critical patent/JPS62133842A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To prevent the deterioration of a bit error rate by inserting a signal point arrangement converter between a differential/rotation object coder and a D/A converter to widen the interval between signal points closest to the boundary of each quadrant. CONSTITUTION:Input data of 4-bit 2-series input data is converted by a binary signal of signal point arrangement to eliminate the phase uncertainty of a recovered carrier in the differential/rotating object coder 1 and the result is fed to a signal point arrangement converter 4. Then the conversion is applied so as to widen the interval between closest signal points to the boundary of each quadrant and the result is inputted to a modulator 3 via a D/A converter 2. The modulator 3 outputs the carrier wave while applying orthogonal amplitude modulation based on the D/A conversion output.

Description

【発明の詳細な説明】 〔概要〕 多値直交振幅変調方式において、再生搬送波の位相不確
定が除去される差動・回転対象符号器とディジタル/ア
ナログ変換器との間に信号点配置変換器を挿入して、各
象限の境界に最も近い信号点の間の間隔を広げてビット
誤り率の劣化を改善する様にしたものである。
[Detailed Description of the Invention] [Summary] In a multilevel orthogonal amplitude modulation system, a signal point arrangement converter is provided between a differential/rotating symmetric encoder and a digital/analog converter that removes phase uncertainty of a reproduced carrier wave. is inserted, and the interval between the signal points closest to the boundary of each quadrant is widened to improve the deterioration of the bit error rate.

〔産業上の利用分野〕[Industrial application field]

本発明は、ディジタルマイクロ波通信に使用する多値直
交振幅変調方式の改良に関するものである。
The present invention relates to an improvement in a multilevel quadrature amplitude modulation method used in digital microwave communications.

近年、各種のディジタルマイクロ波方式、例えば64(
I!L直交振幅変調方式(以下640AM方式と省略す
る)が実用化されているが、周波数利用効率を向上させ
る為に256QAM方式とより多値化の傾向にある。
In recent years, various digital microwave systems, such as 64 (
I! Although the L-quadrature amplitude modulation method (hereinafter abbreviated as 640AM method) has been put into practical use, there is a trend towards 256QAM method and more multilevel modulation in order to improve frequency utilization efficiency.

しかし、多値化が進めば進む程、装置に対する要求性能
が厳しくなるので、装置としては、例えばビット誤り率
の劣化を出来るだけ少なくすることが必要である。
However, as multileveling progresses, the required performance of the device becomes stricter, so it is necessary for the device to minimize deterioration in, for example, bit error rate.

〔従来の技術〕[Conventional technology]

第3図は従来例のブロック図、第4図は第3図の信号点
配置図を示すが、2560静方式の場合を示す。
FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a signal point arrangement diagram of FIG. 3, but shows the case of the 2560 static system.

尚、各信号点の下に記載されている数字は第2ビツト〜
第4ビツトのデータで、各象限の右上の括弧内に記載さ
れている第1ピントの数字を第2ビツトの前に付加した
ものが対応するデータとなる。例えば、A点のデータは
100100と記載されでいるが、第1象限の右上の1
1を付加すると実際は11001100を示す事になる
In addition, the numbers written below each signal point are from the second bit to
The corresponding data is obtained by adding the first focus number written in parentheses at the upper right of each quadrant to the front of the second bit of the fourth bit data. For example, the data for point A is written as 100100, but 1 in the upper right corner of the first quadrant
Adding 1 actually indicates 11001100.

さて、第4図を参照して第3図の動作を説明する。まず
、第3図において、入力される4ビツト2系列(Ich
、  Qch)のデータが差動・回転対象符号器lの中
の差動符号器11に加えられる。
Now, the operation of FIG. 3 will be explained with reference to FIG. First, in FIG. 3, two input 4-bit series (Ich
, Qch) is applied to the differential encoder 11 in the differential/rotating symmetric encoder l.

ここで、昭和60年3月1日企画センタ発行の桑原守二
監修“ディジタルマイクロ波通信”p、106〜107
で示される様に、送信信号の絶対位相を知らなくても正
しいデータを復調できる様に、18号点の位置に情報を
乗せず、位置の遷移に情報を乗せる。
Here, "Digital Microwave Communication" supervised by Moriji Kuwahara, published by Planning Center on March 1, 1985, p. 106-107.
As shown in , information is not placed at the position of point 18, but information is placed at the transition of the position so that correct data can be demodulated without knowing the absolute phase of the transmitted signal.

即ら、差動符号器11でyL = xL ” ’に4の
和分演算を、受信側の差動復号器(図示せず)で糀−’
iJ  lイー(xL +41))’f−1= ”bの
差分演算を行って原信号に変換する事により送信信号の
絶対位相を知る事なしに復調できる。
That is, the differential encoder 11 performs a summation operation of 4 on yL = xL'', and the receiving side differential decoder (not shown) performs the summation operation on
By performing the difference calculation of iJ lE (xL +41))'f-1=''b and converting it to the original signal, demodulation can be performed without knowing the absolute phase of the transmitted signal.

尚、yLは符号器出力、れは符号器入力を示し、和分演
算と差分演算は対の操作であり、両者を合わせて差動変
換と云う。
Note that yL indicates the encoder output, and yL indicates the encoder input. The summation operation and the difference operation are paired operations, and the two are collectively called differential conversion.

次に、差動符号器11の出力は更に回転対象符号器12
に加えられ、第4図に示す様に、第2ビツト〜第4ビツ
トの符号について、各象限の等しい符号が90度間隔に
なる様に配置される。
Next, the output of the differential encoder 11 is further transmitted to a rotationally symmetric encoder 12.
As shown in FIG. 4, the signs of the second to fourth bits are arranged so that the same signs in each quadrant are spaced 90 degrees apart.

例えば、第4図の第4象限の信号点Bは第1象限の信号
点Bと、第1象限の信号点Cは第2象限の信号点Cとそ
れぞれ90度の間隔になっている(第1ビ・7トの符号
を除く)。この為、復調の際に基準搬送波の位相に0.
90.180.270度と90×n度の位相不確定があ
っても、第2〜第4ビツトに変化を生しないので、上記
の差動変換は第1ビツトの信号に対してのみ行えばよく
、第2〜第4ビツトの信号は変換しないでそのまま通過
させる。
For example, signal point B in the fourth quadrant of FIG. (excluding 1-bit and 7-bit codes). Therefore, during demodulation, the phase of the reference carrier wave is 0.
Even if there is a phase uncertainty of 90, 180, 270 degrees and 90 × n degrees, there will be no change in the second to fourth bits, so the above differential conversion can be performed only on the first bit signal. Usually, the second to fourth bit signals are passed through without being converted.

ここで、nは整数を示す。Here, n indicates an integer.

そこで、11001100が回転対象符号器12に入力
すると11111111が出力され、ディジタル/アナ
ログ変換器21.22で最大のアナログ量に変換され、
変調器3で搬送波を直交振幅変調してA点の位置に配置
される。
Therefore, when 11001100 is input to the rotational encoder 12, 11111111 is outputted, which is converted to the maximum analog amount by the digital/analog converter 21.22,
The modulator 3 performs orthogonal amplitude modulation on the carrier wave, and the carrier wave is placed at the position of point A.

以下、入力データは第4図の41号点配置図のそれぞれ
の位置に対応するアナログ量に変換され、第4図に示す
様な位置にそれぞれ配置される。
Thereafter, the input data is converted into an analog quantity corresponding to each position in the point layout diagram No. 41 in FIG. 4, and arranged at the positions shown in FIG. 4, respectively.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ここで、第4図の信号点配置図に示す様に、同−象限内
で、例えば下位3ビツトの信号点D (000010)
が隣りのビット00111帆又は001010に誤って
も1ビツトしか5呉らない。
Here, as shown in the signal point arrangement diagram of FIG. 4, within the same quadrant, for example, the lower 3 bit signal point D (000010)
Even if it is mistaken for the adjacent bit 00111 or 001010, only one bit will be lost.

しかし、象限を越えて誤る時は多ビットの誤りを生ずる
。例えば、第4図の“象限を横切る際の誤り数”の欄に
示す様に最大6ビツト誤ることがある。この為、誤り率
が劣化すると云う問題点がある。
However, when an error occurs beyond the quadrant, a multi-bit error occurs. For example, as shown in the column "Number of errors when crossing quadrants" in FIG. 4, a maximum of 6 bits may be erroneous. Therefore, there is a problem that the error rate deteriorates.

〔問題点を解決する為の手段〕[Means for solving problems]

上記の問題点は、第1図に示す如く、多値直交振幅変調
部に信号点配置変換器4を設け、各象限の境界に最も接
近している信号点の間の間隔を広くしてビット誤り率を
改善する様にした本発明の多植直交振幅変調方式により
解決される。
The above problem can be solved by providing a signal point constellation converter 4 in the multilevel quadrature amplitude modulation section, as shown in FIG. This problem is solved by the multiplant quadrature amplitude modulation method of the present invention, which improves the error rate.

〔作用〕[Effect]

本発明は、各象限の境界に最も接近している信号点の間
の間隔を広くする事により、象限を越えて誤りが発生す
る可能性を減少する様にした。
The present invention reduces the possibility of errors occurring across quadrants by widening the spacing between the signal points closest to the boundaries of each quadrant.

即ち、差動・回転対象符号器1とディジタル/アナログ
変換器2との間に第2図の信号点配置を記taシた信号
点配置変換器4、例えばリード・オ出力を第2図の信号
信号点配置になる様に変換して、ディジタル/アナログ
変換器に加える様にした。そこで、象限を越えて誤る信
号点の数が減るのでビット誤り率が改善される。
That is, a signal point arrangement converter 4 in which the signal point arrangement shown in FIG. I converted it to a signal point arrangement and added it to the digital/analog converter. Therefore, the number of erroneous signal points beyond the quadrant is reduced, so the bit error rate is improved.

〔実施例〕〔Example〕

第1図は本発明の実施例のブロック図、第2図は第1図
の信号点配置図を示し、本発明の実施例で付加された部
分は信号配置変換器4である。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a signal point constellation diagram of FIG. 1. The added part in the embodiment of the present invention is a signal constellation converter 4.

尚、全図を通じて同一記号は同一対象物を示し、256
0計方式の場合を示す。
In addition, the same symbols indicate the same objects throughout the figures, and 256
The case of 0 meter method is shown.

そこで、第2図、第4図を参照しながら、第1図の動作
を説明する。
Therefore, the operation shown in FIG. 1 will be explained with reference to FIGS. 2 and 4.

第1図に示す様に、入力された4ビツト2系列(I c
h、 Qch)のデータは差動・回転対象符号器1で第
4図に示す様な信号点配置になる様な2値の信号に変換
され信号点配置変換器4に加えられる。この信号点配置
変換器は例えば、リード・オンリ・メモリで構成され、
第4図の信号点配置を第2図の信号点配置に変換するデ
ータが書込まれているので、回転対象符号器よりの出力
をアトして第2図に示す様な信号点配置を持つ256Q
AM波が得られる。これにより、ビット誤り率が改善さ
れる。
As shown in FIG. 1, two input 4-bit series (I c
h, Qch) is converted by a differential/rotation symmetric encoder 1 into a binary signal having a signal point arrangement as shown in FIG. 4, and is applied to a signal point arrangement converter 4. This signal point constellation converter is composed of, for example, a read-only memory,
Since the data for converting the signal point arrangement in Figure 4 to the signal point arrangement in Figure 2 is written, the output from the rotational encoder is attenuated to create the signal point arrangement as shown in Figure 2. 256Q
AM waves can be obtained. This improves the bit error rate.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明した様に、各象限の境界に最も接近して
いる信号点の間の間隔を広くしたので、ビット誤り率の
劣化が改善されると云う効果がある。
As explained in detail above, since the interval between the signal points closest to the boundary of each quadrant is widened, there is an effect that the deterioration of the bit error rate is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例のブロック図、第2図は第1図
の信号点配置図、 第3図は従来例のブロック図、 第4図は第3図の信号点配置図を示す。 図において、 1は差動・回転対象符号器、 2はディジタル/アナログ変換器、 3は変調器、 4は信号点配置変換器を示す。 塘2 図 イ逆」Kイダ1のプロ゛・ノフし4 卒  3  ト昌
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a signal point arrangement diagram of Fig. 1, Fig. 3 is a block diagram of a conventional example, and Fig. 4 is a signal point arrangement diagram of Fig. 3. . In the figure, 1 is a differential/rotation symmetric encoder, 2 is a digital/analog converter, 3 is a modulator, and 4 is a signal point constellation converter.塘2 Diagram I Reverse" Kida 1's Pro-Novshi 4 Graduation 3 Tosho

Claims (1)

【特許請求の範囲】 再生キャリアの位相不確定が除去される様に、入力する
複数系列のデイジタル信号を符号化する差動・回転対象
符号部(1)と、 該差動・回転対象符号部の出力をアナログ信号に変換す
るデイジタル/アナログ変換部(2)と、該デイジタル
/アナログ変換部の出力で搬送波を直交振幅変調する変
調器(3)とからなる多値直交振幅変調部において、 各象限の境界に最も接近している信号点の間の間隔を広
げる信号点配置変換器(4)を設け、ビット誤り率を改
善する様にした事を特徴とする多値直交振幅変調方式。
[Claims] A differential/rotating symmetrical code unit (1) that encodes a plurality of input digital signals so that phase uncertainty of a reproduced carrier is removed; and the differential/rotating symmetrical code unit (1). In the multilevel quadrature amplitude modulation section, which includes a digital/analog converter (2) that converts the output of A multilevel orthogonal amplitude modulation system characterized in that a signal point arrangement converter (4) is provided to widen the interval between signal points closest to the boundary of a quadrant, thereby improving the bit error rate.
JP60274003A 1985-12-05 1985-12-05 Multi-value orthogonal amplitude modulation system Pending JPS62133842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60274003A JPS62133842A (en) 1985-12-05 1985-12-05 Multi-value orthogonal amplitude modulation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60274003A JPS62133842A (en) 1985-12-05 1985-12-05 Multi-value orthogonal amplitude modulation system

Publications (1)

Publication Number Publication Date
JPS62133842A true JPS62133842A (en) 1987-06-17

Family

ID=17535592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60274003A Pending JPS62133842A (en) 1985-12-05 1985-12-05 Multi-value orthogonal amplitude modulation system

Country Status (1)

Country Link
JP (1) JPS62133842A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6256357B1 (en) 1992-03-26 2001-07-03 Matsushita Electric Industrial Co., Ltd. Communication system
US6549716B1 (en) 1992-03-26 2003-04-15 Matsushita Electric Industrial Co., Ltd. Communication system
USRE38483E1 (en) 1992-03-26 2004-03-30 Matsushita Electric Industrial Co., Ltd. Communication system
US6724976B2 (en) 1992-03-26 2004-04-20 Matsushita Electric Industrial Co., Ltd. Communication system
US6728467B2 (en) 1992-03-26 2004-04-27 Matsushita Electric Industrial Co., Ltd. Communication system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6256357B1 (en) 1992-03-26 2001-07-03 Matsushita Electric Industrial Co., Ltd. Communication system
US6549716B1 (en) 1992-03-26 2003-04-15 Matsushita Electric Industrial Co., Ltd. Communication system
USRE38483E1 (en) 1992-03-26 2004-03-30 Matsushita Electric Industrial Co., Ltd. Communication system
US6724976B2 (en) 1992-03-26 2004-04-20 Matsushita Electric Industrial Co., Ltd. Communication system
US6728467B2 (en) 1992-03-26 2004-04-27 Matsushita Electric Industrial Co., Ltd. Communication system
USRE39111E1 (en) 1992-03-26 2006-05-30 Matsushita Electric Industrial Co., Ltd. Communication system

Similar Documents

Publication Publication Date Title
JP2845705B2 (en) Multi-level coded modulation communication device
EP0134101B1 (en) Differentially nonlinear convolutional channel coding with expanded set of signalling alphabets
JP2853230B2 (en) Digital filter device
US5168509A (en) Quadrature amplitude modulation communication system with transparent error correction
JPH0642682B2 (en) Error correction multilevel encoding / decoding device
EP0392538B1 (en) Quadrature amplitude modulation communication system with transparent error correction
CA2088062C (en) Coded qam system
KR100195177B1 (en) Trellis coded modulation system
US5757856A (en) Differential coder and decoder for pragmatic approach trellis-coded 8-PSK modulation
JPH0370420B2 (en)
JPS62133842A (en) Multi-value orthogonal amplitude modulation system
EP0348968A3 (en) Multilevel quadrature amplitude modulator capable of reducing a maximum amplitude of a multilevel quadrature amplitude modulated signal regardless of transmission data information or redundant information
US6370201B1 (en) Simplified branch metric calculation in pragmatic trellis decoders
JPS60134545A (en) Data communication signal structure
EP0588387B1 (en) D/A converter capable of producing an analog signal having levels of a preselected number different from 2**N and communication network comprising the D/A converter
JPH0122787B2 (en)
JP2548932B2 (en) Multilevel QAM communication system
US3821481A (en) Three channel psk data modem apparatus
JPH0443448B2 (en)
JP3313400B2 (en) Coded multi-level modulator
JPS6339239A (en) Encoing, modulating and demodulating circuit
JPH0648830B2 (en) Modulator
JPH022277A (en) Multi-value qam communication system
JP2723002B2 (en) Uncoded level signal judgment circuit
JPS5823022B2 (en) Differential encoding method