JPS5966137A - Wire bonding method - Google Patents

Wire bonding method

Info

Publication number
JPS5966137A
JPS5966137A JP57176179A JP17617982A JPS5966137A JP S5966137 A JPS5966137 A JP S5966137A JP 57176179 A JP57176179 A JP 57176179A JP 17617982 A JP17617982 A JP 17617982A JP S5966137 A JPS5966137 A JP S5966137A
Authority
JP
Japan
Prior art keywords
bonding
wire
wire bonding
bonded
reliability
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57176179A
Other languages
Japanese (ja)
Inventor
Jun Morishita
順 森下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP57176179A priority Critical patent/JPS5966137A/en
Publication of JPS5966137A publication Critical patent/JPS5966137A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the waste of a wire material for wiring, and the number and time of bonding, and to improve the yield of an external appearance and the reliability of a wire bonding method by selectively wire bonding only a bonding pad used for inputting/outputting and a conductive part. CONSTITUTION:A wire 5 is not bonded to unused bonding pads A, E and an inner lead 4 corresponding thereto, but selectively bonded only to bonding pads B, C, D used for inputting/outputting. Since such a selective wire bonding can be readily executed for each type of pellets 1 by using a coordinate recognition of bonding with an RAM system or the like, wire material can be saved, the number of bonding steps and time can be shortened, and the yield of an external appearance and reliability can be improved.

Description

【発明の詳細な説明】 本発明はワイヤボンディング方法に関するものである。[Detailed description of the invention] The present invention relates to a wire bonding method.

一般に、集積回路（ＩＣ）や大規模集積回路（ＬＳＩ）
の如き半導体製品の組立過程においては、リードフレー
ムのタブ等のペレット付は面にベレットをボンディング
した後、ペレットのポンディングパッドをリードフレー
ムのインナーリード等の入出力端子への導電部と金（Ａ
ｕ）またはアルミニウム（Ａ２）等のワイヤでボンディ
ングして電気的に接続している。Generally, integrated circuits (IC) and large-scale integrated circuits (LSI)
In the assembly process of semiconductor products such as lead frame tabs, etc., after bonding the pellet to the surface of the lead frame, the pellet's bonding pad is connected to the conductive part and gold ( A
They are electrically connected by bonding with wires such as u) or aluminum (A2).

ところで、このような場合、従来はＲＯＭ（読出し専用
メモリ）を座標認識のために使用し、第１図に示すよう
に、ペレット１の入出力用のポンディングパッド２．３
の全部をリードフレームのインナーリード４と無差別に
ワイヤ５をボンディングしている。By the way, in such a case, conventionally, a ROM (read-only memory) is used for coordinate recognition, and as shown in FIG.
The wires 5 are indiscriminately bonded to the inner leads 4 of the lead frame.

しかし、半導体製品の種類によっては、たとえばユーザ
ーの用途に応じて入出力仕様の異なるゲートアレイ、マ
スクスライスＬＳＩ等のように、予め用意されている入
出力を全部は使用しない場合がある。However, depending on the type of semiconductor product, for example, gate arrays, mask slice LSIs, etc., which have different input/output specifications depending on the user's application, not all of the input/outputs prepared in advance may be used.

したがって、このような場合にも全部のポンディングパ
ッドとインナーリード等の導電部とを無差別にワイヤボ
ンディングするのでは、金やアルミニウムの如き高価な
配線用ワイヤ材料の無駄。Therefore, even in such a case, if all bonding pads and conductive parts such as inner leads are wire-bonded indiscriminately, expensive wiring wire materials such as gold and aluminum are wasted.

外観歩留ｐや信頼度の低下を来たし、不要なボンディン
グを行なうことによるボンディング工数と時間の浪費に
もなってしまう。特に、集積度の増大により入出力数が
増加する傾向に伴なって、この問題はますます大きくな
シ９つある。This results in a decrease in appearance yield and reliability, and unnecessary bonding results in a waste of bonding man-hours and time. In particular, this problem is becoming more and more serious as the number of inputs and outputs tends to increase due to increased integration.

本発明の目的は、前記従来技術の問題点を解消し、配線
用ワイヤ材料の無駄、ボンディング工数と時間の低減、
外観歩留りおよび信頼度の向上を図ることのできるワイ
ヤボンディング方法を提供することにある。It is an object of the present invention to solve the problems of the prior art, reduce waste of wiring wire materials, reduce bonding man-hours and time,
It is an object of the present invention to provide a wire bonding method capable of improving appearance yield and reliability.

以下、本発明を図面に示す一実施例にしノこかって詳細
に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to an embodiment shown in the drawings.

第２図は本発明のワイヤボンディング方法によシベレッ
トのポンディングパッドとリードフレームのインナーリ
ードとにワーｒヤをボンディングしたー実施例、を示す
概略的部分平面図である。FIG. 2 is a schematic partial plan view showing an embodiment in which a wire is bonded to a bonding pad of a Siberette and an inner lead of a lead frame by the wire bonding method of the present invention.

この実施例においでは、ペレット１のボンディングバン
ド２．３のうち、入力用のボンディングバンド２のうち
のボンディングバンドＡ、および出力用のボンディング
バンド３のうちのポンディングパッドＥはペレット１内
のどの回路とも接続されていない不使用パッドである。In this embodiment, of the bonding bands 2.3 of the pellet 1, the bonding band A of the input bonding band 2 and the bonding pad E of the output bonding band 3 are located at which part of the pellet 1. This is an unused pad that is not connected to any circuit.

このような不使用のボンディングバンドＡ、Ｅは、ゲー
トアレイやマスタスライスＬＳＩのように、予めペレッ
ト１内に配置された論理を配線パターンによっ′Ｃ多品
種に展開して行くものにおいては品種によって生じ、平
均全ボンディングバンドの１割程度になる場合もある。Such unused bonding bands A and E are used in devices such as gate arrays and master slice LSIs in which logic previously placed in the pellet 1 is expanded into various types by wiring patterns. In some cases, the average bonding band is about 10% of the total bonding band.

そこで、本実施例では、ワイヤボンディングの座標認識
にたとえばＲＡ　Ｍ　（ランダムアクセスメモリ）方式
を用いることによシ、不使用のボンディングバンドＡ、
Ｅおよびそれらに対応するインナーリード４にはワイヤ
５をボンディングせず、入出力のために用いられている
ボンディングバンドＢ、Ｃ，Ｄにのみ選択的にワイヤ５
をボンディングしている。Therefore, in this embodiment, by using, for example, a RAM (random access memory) method for wire bonding coordinate recognition, unused bonding bands A,
Wires 5 are not bonded to E and their corresponding inner leads 4, and wires 5 are selectively bonded only to bonding bands B, C, and D used for input/output.
are bonded.

このような選択的なワイヤボンディングは前記の如くボ
ンディングの座標認識にＲＡＭ方式等を用いれば、ペレ
ット１０品種毎に容易に行なうことができる。Such selective wire bonding can be easily performed for every 10 types of pellets by using a RAM system or the like to recognize the bonding coordinates as described above.

したがって、本実施例においては、ワイヤボンディング
不要のボンディングバンドおよびインナーリードへのワ
イヤボンディングを省略できることによシ、ワイヤ材料
を節約でき、ボンディングの工数低減と時間短縮が可能
でおる上に、外観歩留りや信頼度を向上させることがで
きる。Therefore, in this embodiment, by omitting wire bonding to the bonding band and inner leads that do not require wire bonding, it is possible to save wire materials, reduce the number of bonding steps and time, and improve the appearance yield. and reliability can be improved.

特に、本発明は多ピン化、高集積度化が進んだ半導体製
品に通用すれば、極めて大きい効果を得ることができる
。In particular, if the present invention is applied to semiconductor products with increased pin count and higher degree of integration, extremely large effects can be obtained.

以上説明したように、本発明によｊｔは、配線用ワイヤ
材料の節約によるコストの低減、ボンディング工数の低
減とボンディング時間の短縮、外観歩留シおよび信頼度
の向上を図ることができる。As explained above, the JT according to the present invention can reduce costs by saving wiring wire materials, reduce bonding man-hours and bonding time, and improve appearance yield and reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のワイヤボンディングの様子を示す概略的
部分平面図、 第２図は本発明によるワイヤボンディング方法の一実施
例を示す概略的部分平面図である。 １・・ペレット、２，３・・・ボンディンクハソド。 ４・・・リードフレームのインナーリード、５・・・ワ
イヤ。 第　　１　　図 ／ ７２図FIG. 1 is a schematic partial plan view showing a state of conventional wire bonding, and FIG. 2 is a schematic partial plan view showing an embodiment of the wire bonding method according to the present invention. 1... Pellet, 2, 3... Bondink Hasod. 4... Inner lead of lead frame, 5... Wire. Figure 1/Figure 72

Claims (1)

【特許請求の範囲】[Claims] １、ベレットのポンディングパッドと入出力端子への導
電部との間にワイヤをボンディングする方法において、
入出力のだめに使用されるポンディングパッドと導電部
のみに選択的にワイヤボンディングすることを特徴とす
るワイヤボンディング方法。1. In the method of bonding a wire between the bullet's bonding pad and the conductive part to the input/output terminal,
A wire bonding method characterized by selectively wire bonding only to bonding pads and conductive parts used for input/output terminals.
JP57176179A 1982-10-08 1982-10-08 Wire bonding method Pending JPS5966137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57176179A JPS5966137A (en) 1982-10-08 1982-10-08 Wire bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57176179A JPS5966137A (en) 1982-10-08 1982-10-08 Wire bonding method

Publications (1)

Publication Number Publication Date
JPS5966137A true JPS5966137A (en) 1984-04-14

Family

ID=16009034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57176179A Pending JPS5966137A (en) 1982-10-08 1982-10-08 Wire bonding method

Country Status (1)

Country Link
JP (1) JPS5966137A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279658A (en) * 1975-12-25 1977-07-04 Citizen Watch Co Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279658A (en) * 1975-12-25 1977-07-04 Citizen Watch Co Ltd Semiconductor device

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