JPS63234538A - Chip for semiconductor device - Google Patents

Chip for semiconductor device

Info

Publication number
JPS63234538A
JPS63234538A JP62069624A JP6962487A JPS63234538A JP S63234538 A JPS63234538 A JP S63234538A JP 62069624 A JP62069624 A JP 62069624A JP 6962487 A JP6962487 A JP 6962487A JP S63234538 A JPS63234538 A JP S63234538A
Authority
JP
Japan
Prior art keywords
semiconductor device
chip
pads
pair
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62069624A
Other languages
Japanese (ja)
Inventor
Hideto Nitta
新田　秀人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62069624A priority Critical patent/JPS63234538A/en
Publication of JPS63234538A publication Critical patent/JPS63234538A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

PURPOSE:To inhibit the lowering of the assembly yield of a semi conductor device and to contrive an increase in the density of the device by a method wherein a chip for the semiconductor device is provided with a pair of adjacent pads which are electrically connected to each other through a prescribed gold ball. CONSTITUTION:A chip 3 for a semiconductor device is provided with inner pads 1 to be used as ones for wire bonding and a pair of adjacent pads 2, wires 4 which are connected to external wire bonding areas to correspond to the pads 1 are each wire-bonded to the respective inner pad 1 and a pair of the adjacent pads 2 are electrically connected to each other through a gold ball 5. Accordingly, such an execution as the setting of prescribed electrical conditions can be performed without the mediation of external terminals and the number of the bonding wires which are connected to the external wire bonding areas is reduced. Thereby, with the assembly yield of the semiconductor device improved, an increase in the density of the device can be contrived.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用チップに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a chip for a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、半導体装置に用いられる半導体装置用チップとし
ては、パターン形成された半導体装置用チップをリード
フレームにマウントし、半導体装置用チップのボンディ
ング用パッド（以下、インナーパッドと言う）とリード
フレームのボンディングエリアとをワイヤボンディング
によって接続し、トランスファーモールド封止を行い、
リードフレームの切断加工を施して半導体装置を形成す
る方法に対応して用いられるのが一般である。Conventionally, as a semiconductor device chip used in a semiconductor device, a patterned semiconductor device chip is mounted on a lead frame, and bonding between a bonding pad (hereinafter referred to as an inner pad) of the semiconductor device chip and the lead frame is performed. Connect the area with wire bonding, perform transfer mold sealing,
It is generally used in accordance with a method of cutting a lead frame to form a semiconductor device.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置用チップは、前記半導体装置
用チップの有する電気的機能が、前記半導体装置用チッ
プのインナーパッドからホンディングワイヤを介して外
部端子に取出されるのが一般的であり、前記電気的機能
において、例えばある初期条件を設定する場合には前記
外部端子を介して行うことが必要となる。In the conventional semiconductor device chip described above, the electrical function of the semiconductor device chip is generally taken out from the inner pad of the semiconductor device chip to an external terminal via a bonding wire, In the electrical function, for example, when setting a certain initial condition, it is necessary to set it via the external terminal.

しかしながら、例えば複数の半導体チップをセラミック
基板に搭載し、ワイヤボンディングにより回路形”成を
行ういわゆるハイブリッドＩＣにおいて、より高密度組
立てを要する場合、またはインナーパッドの多い半導体
装置用チップ等の場合には、インナーパッドからのボン
ディングワイヤの数が多くなるため、結果的に組立歩留
りの低下を招くという欠点があり、また、インナーパッ
ドに接続される例えばセラミック基板上のワイヤボンデ
ィングエリアの占有面積も拡大するため、半導体装置の
高密度化を阻害するという欠点がある。However, for example, in the case of a so-called hybrid IC in which multiple semiconductor chips are mounted on a ceramic substrate and a circuit is formed by wire bonding, which requires higher density assembly, or in the case of a semiconductor device chip with many inner pads, etc. , since the number of bonding wires from the inner pad increases, the assembly yield is reduced as a result, and the area occupied by the wire bonding area on, for example, a ceramic substrate connected to the inner pad also increases. Therefore, there is a drawback that it impedes higher density of semiconductor devices.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置用チップは、所定の金球を介して、
電気的に相互間の接続が行われる少くとも一対の隣接す
るパッドを備えて構成される。The chip for a semiconductor device of the present invention has the following properties:
The pad includes at least a pair of adjacent pads that are electrically connected to each other.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の平面図である。第１図に示
されるように、本実施例の半導体装置用チップ３は、ワ
イヤボンディング用として用いられるインナーパッド１
と、一対の隣接するパッド２と、を備えており、それぞ
れのインナーパッド１には、対応する外部のワイヤボン
ディングエリア（図示されない）に連結されるワイヤ４
がワイヤボンティングされ、また、一対の隣接するパッ
ド２は、金球５によって電気的に接続されている。FIG. 1 is a plan view of one embodiment of the present invention. As shown in FIG. 1, the semiconductor device chip 3 of this embodiment has an inner pad 1 used for wire bonding.
and a pair of adjacent pads 2, each inner pad 1 having a wire 4 connected to a corresponding external wire bonding area (not shown).
are wire-bonded, and a pair of adjacent pads 2 are electrically connected by a gold ball 5.

第１図において、本発明の特徴である隣接するパッドを
金球５によって電気的に接続することにより、半導体装
置用チップ３の有する電気的機能の一部、例えば所定の
電気的条件設定等の実行が、従来性われている外部端子
を介することなしに行われる。従って、インナーパッド
を介して外部のワイヤボンディングエリアに連結される
ボンディングワイヤの数量が低減される。In FIG. 1, by electrically connecting adjacent pads with gold balls 5, which is a feature of the present invention, some of the electrical functions of the semiconductor device chip 3, such as setting predetermined electrical conditions, can be performed. Execution takes place without conventional external terminals. Therefore, the number of bonding wires connected to the external wire bonding area via the inner pad is reduced.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は半導体装置用チップの内
部に金球にて接続可能な隣接するパッドを少なくとも１
対具備し、前記金属球を介して半導体装置用チップの内
部にて所定の電気的機能を形成させることにより、前記
半導体装置用チップの外部に対するボンディングワイヤ
の数量を少なくすることが可能となり、半導体装置の組
立歩留りの低下が改善されるとともに、半導体装置の高
密度化を計ることが可能になるという効果がある。As explained above, the present invention provides at least one adjacent pad that can be connected with a gold ball inside a chip for a semiconductor device.
By forming a predetermined electrical function inside the semiconductor device chip via the metal ball, it is possible to reduce the number of bonding wires to the outside of the semiconductor device chip. This has the effect of not only improving the reduction in device assembly yield but also making it possible to increase the density of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の平面図である。 図において、１・・・インナーパッド、２・・・隣接し
たパッド、３・・・半導体装置用パッド、４・・・ワイ
ヤ、５・・・金球。FIG. 1 is a plan view of one embodiment of the present invention. In the figure, 1... Inner pad, 2... Adjacent pad, 3... Pad for semiconductor device, 4... Wire, 5... Gold ball.

Claims (1)

【特許請求の範囲】[Claims] 　所定の金球を介して、電気的に相互間の接続が行われ
る少くとも一対の隣接するパッドを備えることを特徴と
する半導体装置用チップ。1. A chip for a semiconductor device, comprising at least a pair of adjacent pads that are electrically connected to each other through a predetermined gold ball.
JP62069624A 1987-03-23 1987-03-23 Chip for semiconductor device Pending JPS63234538A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62069624A JPS63234538A (en) 1987-03-23 1987-03-23 Chip for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62069624A JPS63234538A (en) 1987-03-23 1987-03-23 Chip for semiconductor device

Publications (1)

Publication Number Publication Date
JPS63234538A true JPS63234538A (en) 1988-09-29

Family

ID=13408208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62069624A Pending JPS63234538A (en) 1987-03-23 1987-03-23 Chip for semiconductor device

Country Status (1)

Country Link
JP (1) JPS63234538A (en)

Similar Documents

Publication Publication Date Title
US5373188A (en) Packaged semiconductor device including multiple semiconductor chips and cross-over lead
US6781240B2 (en) Semiconductor package with semiconductor chips stacked therein and method of making the package
KR100369907B1 (en) Semiconductor Package And Mounting Structure On Substrate Thereof And Stack Structure Thereof
JPH1012769A (en) Semiconductor device and its manufacture
JP4146290B2 (en) Semiconductor device
JP2809945B2 (en) Semiconductor device
JP2001156251A (en) Semiconductor device
JPS6028256A (en) Semiconductor device
JPH0783035B2 (en) Semiconductor device
JPH0194636A (en) Semiconductor device
US6642735B2 (en) Semiconductor package for chip with testing contact pad connected to outside
JPS63234538A (en) Chip for semiconductor device
JPH05235245A (en) Semiconductor integrated circuit device
JPH0256942A (en) Semiconductor device
JP3234614B2 (en) Semiconductor device and manufacturing method thereof
JPH0461152A (en) Semiconductor device
JP2913858B2 (en) Hybrid integrated circuit
KR100258607B1 (en) Chip scale semiconductor package of lead on chip type and method for manufacturing the same
JPH0287635A (en) Ceramic package semiconductor device
KR20040013736A (en) Method of manufacturing semiconductor package
JPH05291345A (en) Semiconductor device
JPS5828359Y2 (en) Semiconductor integrated circuit device
JPH08130286A (en) Semiconductor device
JPH02156662A (en) Resin-sealed semiconductor device
JPS6151953A (en) Semiconductor device