JPS5965464A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To stop the flow of excessive current when power source is connected reversely by a method wherein the base region of a P-N-P transistor, having an emitter region circuit connected to the power source side, and a collector region are connected to the collector region of the P-N-P transistor formed by performing a P-N junction isolation, thereby enabling to have a circuit connection in invertedly biased direction. CONSTITUTION:The elements illustrated on the right side of the diagram A and B are N-P-N transistors, and the elements illustrated on the left side are P-N-P transistors. The collector of the N-P-N transistor is connected to an N type region 71 and a P type region 51 using a wiring 92, and a P type region 52 is connected to the power source 12. When the positive electrode of the power source is erroneously connected to a substrate 1 and the negative electrode is erroneously connected to a wiring 94, the P-N junction formed by the P type region 52 and an N type epitaxial layer 31 is biased invertedly. The withstand voltage of said P-N junction is designed in such a manner that it becomes higher than the supply voltage used. Thus, the P-N junction formed by the region 52 and an epitaxial layer 31 maintains the applied voltage, and an excessive current runs when erroneously connected, thereby enabling to prevent the trouble such as the destruction of an integrated circuit and a power source.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to one having a built-in protection means for preventing damage to the semiconductor integrated circuit and the power supply when an applied power supply terminal is incorrectly connected.

Conventional configurations and their problems A bipolar semiconductor integrated circuit is a circuit in which a large number of elements such as transistors, diodes, and resistors are formed on a single silicon chip, and these are interconnected to perform the desired circuit function. However, as a method for separating these elements, PN junction separation is currently widely used.

The structure of this method is shown in FIG. That is, FIG. 1 shows PN junction isolation using an N P N transistor used in a semiconductor integrated circuit as an example. FIG. 1 (8) is a plan view, and FIG. -x' sectional view.

In the figure, 1 is a P-type substrate, 2 is an N-type buried diffusion region diffused on the P-type substrate 1 to lower the collector resistance of the transistor, and 3 is the N-type buried diffusion region 2 formed thereon. After that, an N-type epitaxial layer is formed on the entire surface of the substrate by epitaxial growth technology and becomes the collector of the NPN transistor; 4 is a P-type isolation diffusion region introduced to separate each element; 5 is a P-type base diffusion region; 6 is an emitter diffusion region formed in the P-type base diffusion region 6; 7 is an N-type diffusion region provided in the collector to make contact with the electrode; 8 is a silicon oxide film; 91, 92, 93;
are the emitter collector and base electrodes, respectively.

By the way, the P-type isolation region 4 and the P-type substrate 1 are connected to the lowest potential in the integrated circuit, and the regions 2 and the epitaxial layer 3 are biased in the opposite direction, so that each element is electrically isolated. It will be done.

In an integrated circuit, the lowest potential is usually connected to the negative electrode of an externally applied power supply, and the highest potential is connected to the positive electrode, and each element operates between these potentials.

Although a variety of circuit configurations are used in integrated circuits, some circuit configurations often connect the collector electrode 92 of the transistor (NPN) directly to a power source and extract the electrical signal from the emitter electrode 91. However, with this circuit configuration, if the positive and negative electrodes of the power supply are connected incorrectly, the first
Since a positive electrode is connected to the P-type substrate 1 and P-type isolation region 4 in the figure, and a negative electrode is connected to the region 2° epitaxial layer 3, the PN junction is forward biased and an excessive current flows, causing the integrated circuit and There were concerns that the power supply would be destroyed.

OBJECTS OF THE INVENTION The present invention provides a semiconductor integrated circuit device having a protection means for avoiding the inconvenience of destruction of the integrated circuit and the power supply when the power supply terminal to the integrated circuit is incorrectly connected.

Structure of the Invention The present invention provides a semiconductor integrated circuit device in which the base region and collector region of a PNP transistor whose emitter region is circuit-connected to the power supply side are connected to the collector region of an NPN transistor formed by PN junction separation. It is. According to this, even when the power supply is reversely connected, the PNP
) The transistor is connected to the circuit in the reverse bias direction, which acts to prevent excessive current.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows a semiconductor integrated circuit device which is an embodiment of the present invention. is its equivalent circuit diagram.

In the figure, 1 is a P-type substrate, 2 and 21 are N-type buried diffusion regions, 3 and 31 are N-type epitaxial layers, 4 is a P-type isolation diffusion region, 6 and 61.62 are P-type diffusion regions, 61 is 6
7. a P-type diffusion region formed in a relationship surrounding 2; 1st
is an N-type diffusion region, 8 is a silicon oxide film, 91.92, 9
3.94 is a wiring, and 94 is connected to a power supply. That is, the elements on the right in FIGS. 2A and 2B are the NPN transistors illustrated in FIG. 1, and the elements on the left are PNP transistors often used in semiconductor integrated circuits.

The collector of the (NPN) transistor is connected to the N-type region 71 and the P-type head region 61 by a wiring 92, and the P-type region 52 is connected to the stain source 12 by a wiring 94.

In the semiconductor device of this embodiment, if the positive electrode of the power source is mistakenly connected to the substrate 1 side and the negative electrode is connected to the wiring 94,
The P type region 52 and the N type epitaxial layer 31 form
The N junction is biased in the opposite direction. The breakdown voltage of this PN junction is designed to be higher than the power supply voltage used. The reason for this is that although the region 52 and the epitaxial layer 31 are formed at the same time as the region 6 and the epitaxial layer 3 of the NPN transistor, that is, the base and collector, normal power supply connection is possible if the withstand voltage between the base and collector is lower than the power supply voltage. This is because sometimes the N'P N ) transistor has insufficient withstand voltage, and stable circuit operation cannot be expected.

Thus, the PN junction formed between the region 62 and the epitaxial layer 31 supports the applied voltage, and in the event of a misconnection, an excessive current flows.
This prevents the inconvenience of destroying the integrated circuit and power supply.

This relationship is shown in an equivalent circuit diagram as shown in Fig. 2 (NPN as in q). Since the base potential is at most the power supply voltage, the operating voltage range of the emitter will not be narrowed.

Effects of the Invention As described above, the present invention is capable of protecting integrated circuits and power supplies from destruction due to excessive current when power terminals are incorrectly connected without any adverse effect on circuit operation, and is simple and practical. The present invention provides a semiconductor integrated circuit device having effects.

[Brief explanation of drawings]

Figure 1 is a structural diagram of a bipolar semiconductor integrated circuit using PN junction isolation.
-x' sectional view, Figure 2 is a diagram showing an embodiment of the present invention, figure (5) is a plan view, figure (B) is its Y-Y' sectional view,
The same figure (q is its equivalent circuit diagram. 1... P type substrate, 2, 21... N type buried diffusion region, 3, 31... N type Epitaxial layer, 4...P type isolation diffusion region, 5, 51.52
...P-type diffusion region, 6, 7, 71...
...N-type diffusion region, 8...Silicon oxide film, 9
1.92,93.94...Wiring, 12...
··power supply.

Claims (1)

Claims: An NPN) transistor and a PNP) transistor formed by PN junction isolation, the emitter of the PNP transistor being connected to a power supply, and the base and collector of the PNP transistor being connected in common. 1. A semiconductor integrated circuit device, characterized in that a point is connected to a resistor of the NPN transistor.