JPS5965452A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To supress generation of gap to be easily formed between layers, uniformly form an inter-layer insulating film and improve inter-layer insulating strength by depositing a thin polycrystalline silicon film on the entire part of main surface including the first polycrystalline silicon film and by oxidizing it in manufacture of double-layer polycrystalline silicon. CONSTITUTION:A silicon dioxide film 3 and a silicon nitride film 4 are formed, a first polycrystalline silicon film 5 is formed by growth method, a polycrystalline silicon film 13 is deposited by etching and it is oxidized. An inter-layer inslating film 14 and a silicon dioxide film 15 are formed uniformly by the growth method. Thereby, abnormality at the end part can be improved drastically. Moreover, growth of grain of polycrystalline silicon film 5 and generation of protrusion can also be reduced considerably. The silicon dioxide film 15, a silicon nitride film 4 and a silicon dioxide film 3 are removed by the etching, a second gate oxide film 7, a second polycrystalline silicon film 8 are formed by growth method, and a pattern is also formed. Shape of the overlapping region of the first and second polycrystalline silicon films 5, 8 are improved and an interlayer insulating film 14 is formed uniformly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention is directed to improving the interlayer dielectric breakdown voltage of the two layers of polycrystalline silicon and the first The present invention relates to a method for manufacturing a semiconductor device, which improves the step shape of a polycrystalline silicon layer, thereby making it possible to prevent disconnections and bridges in aluminum wiring, etc.

Conventional configurations and their problemsRecently, large capacity MOS dynamic memories (K collection &
ft), there is a demand for a reduction in memory cell size, but the increase in memory cell capacity, so-called high integration, cannot be reduced in proportion to the reduction in memory cell size due to operational reasons. In conjunction with the reduction of the memory plus the size, it becomes necessary to thin the insulating film in the capacitor portion that constitutes the memory cell. Conventionally, thermal oxide films commonly used as insulating films have been able to form uniform, high-quality films up to a film thickness of about 1000 yen, but when the film thickness becomes thinner than this, pinholes are likely to occur. The film quality deteriorates significantly. Also, polycrystalline silicon', l! il A411i
2-layer game using point metal etc. for gate electrode 1j"Jr'
ja, the second gate oxide film also becomes thinner as the gate length is reduced. For example, in a two-layer polycrystalline silicon gate electrode structure, the interlayer insulating film between the two-layer gate formed of first and second polycrystalline silicon is formed by thermal oxidation of the substrate to form an insulating film under the second gate electrode. At the same time, it was formed by oxidizing the surface portion of the first polycrystalline silicon film, but if the second gate oxide film becomes thin, this process cannot be used. In response to miniaturization, the insulating film constituting the capacitive part of the memory cell has a two-layer structure of silicon dioxide and a silicon tinodide film, which is a high dielectric constant, and the interlayer insulating film between the polycrystalline silicon layers has a thickness of at least 2° There are also requests for a range of 300 nm to 300 nm. However, in the conventional method, it is difficult to form a thick interlayer insulating film as described below. That is, a conventional 2M polycrystalline silicon structure will be taken as an example.

FIG. 1 shows a cross-sectional view of a two-layer polycrystalline silicon structure in an ideal state. In the figure, 1 is a semiconductor substrate, 2 is a silicon dioxide film formed by a selective oxidation method, and 3.4 is an insulating film constituting a capacitor part of a memory cell. It is a two-layer insulating film made of silicon oxide film. 5 is a first electrode made of a single-layer polycrystalline silicon film; 6 is an interlayer insulating film; 7 is a second gate-oxide film; 8 is a second electrode made of a second-layer polycrystalline silicon film; 9 is an N+ diffusion layer, 1o is an interlayer insulating film, 11 is an aluminum electrode, and 12 is a protective film for the element.

Next, a process for forming an interlayer insulating film of this semiconductor device will be explained with reference to FIGS. 2(a) to 2(d). First, as shown in FIG. 2(a), a field oxide film 2 is formed on a semiconductor substrate 1 by a selective oxidation method, a silicon dioxide film 3, a silicon tinide film 4, and a polycrystalline silicon film 6 are sequentially deposited. Phosphorus is evaporated onto the crystalline silicon film 6, and the sheet resistance is set to about 40Ω/hole by thermal diffusion.

Next, as shown in FIG. 2(b), the polycrystalline silicon film 6 is patterned into the shape of the first electrode by photolithography, and then the surface of the polycrystalline silicon film 6 is thermally oxidized to form a silicon dioxide film. form 6. Since the other parts are covered with the silicon nitride film 4, no oxide film grows. When the polycrystalline silicon film 5 is oxidized, the surface of the polycrystalline silicon film is not oxidized uniformly, and the edges A and B are located at the boundary between the polycrystalline silicon film 6 and the silicon tinide film 4, as shown in the figure. Areas where the oxide film is susceptible to slipping occur, creating gaps. This phenomenon occurs more easily as the oxide film thickness of the polycrystalline silicon film becomes thicker, and larger gaps are created. This gap becomes somewhat less likely to occur when oxidized at high temperatures, but at high temperatures, the dale size of polycrystalline silicon increases and protrusions are generated on the surface, which can cause oxide film defects. Another problem is that the insulation performance between the second polycrystalline silicon layers is significantly reduced. Furthermore, in the next step to form the second gate insulating film,
When the silicon nitride film 4 and the silicon dioxide film 3 are removed, the etching solution enters into this gap, and the thickness of the silicon dioxide film 6 in this part becomes even thinner, further reducing the interlayer insulation. Further, such a portion has poor cleaning effect and causes deterioration of characteristics.

Next, as shown in FIG. 2(C), thermal oxidation is performed to form the second gate insulator M7, and then a second layer polycrystalline silicon film 8 is deposited, and like the first layer polycrystalline silicon, phosphorus vapor deposition is performed. ,
Performs heat diffusion. In this step, the interlayer dielectric strength voltage between the polycrystalline silicon films 5 and 8 decreases at the part A in FIG. 2(b),
Show 1- also becomes more likely to occur. Furthermore, etching remains of the second layer of polycrystalline silicon in the gap at part B in Fig. 2(b)! 1187 is likely to occur, and bridging of the second layer polycrystalline silicon film 8 occurs in this portion.

Next, as shown in FIG. 2(d), an N+ diffusion region 9, an interlayer insulating film 10, and an aluminum electrode 11 are formed.

As described above, M with the conventional two-layer polycrystalline silicon structure
In the O8 integrated circuit device, the above-mentioned problem cannot be avoided in the process of forming an interlayer insulating film as the pattern becomes finer.

Purpose of the Invention Therefore, the present invention makes it possible to uniformly form an interlayer insulating film between two layers of polycrystalline silicon, improve the interlayer dielectric breakdown voltage, and improve the shape of the side surface of the first polycrystalline silicon. A method for manufacturing a semiconductor device is provided.

Composition of the invention The present invention provides a silicon dioxide film on one main surface of a semiconductor substrate.

A step of stacking silicon nitride films to form a two-layer insulating film, a step of depositing a first polycrystalline/recon film on the two-layer insulating film, and depositing the first polycrystalline silicon film in a predetermined manner. forming a pattern in the shape of one electrode; depositing a polycrystalline silicon film thinner than the first polycrystalline silicon film over the entire main surface side including the first electrode; A method for manufacturing a semiconductor device, comprising a step of oxidizing a surface layer of a first polycrystalline silicon film, a step of depositing a second polycrystalline silicon film on the entire surface, and patterning it in the shape of a second electrode, By this, the first electrode and the second
It is possible to suppress the occurrence of gaps that are likely to be formed between layers with electrodes, and eliminate the cause thereof.

DESCRIPTION OF EMBODIMENTS In the following, the present invention will be described in more detail with reference to embodiments.
Figures a) to (q) are manufacturing process flowcharts showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention. In FIG. 3(a), 1 is a -P type silicon substrate, and 2 is a field oxide film formed by selective oxidation. Next, as shown in FIG. 3(b), a silicon dioxide film 3 and a silicon nitride film 4 constituting a gate insulating film are formed, and then a first polycrystalline silicon film 5 is grown to a length of 5001 m, and then phosphorus is added to this film. By vapor deposition, the sheet resistance of the polycrystalline silicon film 5 is set to 400/unit. Next, this first polycrystalline silicon film 5 is formed into a turn by photolithography using a resin. Only the polycrystalline silicon film 5 is etched, leaving the silicon tinide film 4. Then, as shown in FIG. C) No. 1]<, a thin polycrystalline silicon film 13 of about 10 nm is applied to the entire main surface side.
accumulate. This is subjected to wet oxidation at surprisingly high pressure at 28 degrees Celsius to form an interlayer insulating film 14 of 30°C, as shown in Figure 3(d).
grow by nm. 1 In this process, a thin polycrystalline silicon film 1
3 are all oxidized, and about 200 silicon dioxide films 15 are grown on the silicon tinide film 4 where the first polycrystalline silicon film 5 is not present. In the conventional method, only the surface of the first polycrystalline silicon was oxidized, but it was not oxidized uniformly, and a thin oxide film was formed at the edges. By depositing the silicon film 13, the oxide films 14 and 15 grow uniformly, and abnormalities at the edges are significantly improved. Furthermore, the effect of significantly reducing the growth of duplexes and the generation of protrusions in the polycrystalline silicon film 5 can be seen. Note that the occurrence of these protrusions is influenced by the phosphorus concentration of polycrystalline silicon, oxidation humidity, etc. Low-temperature, high-pressure oxidation is more effective than high-temperature acid oxidation at normal pressure. Next, the silicon dioxide film 16 is removed by etching the oxide film over the entire surface. Further, after that, using the silicon dioxide film 14 as a mask,
The exposed portion of the silicon nitride film 4 is removed by plasma etching using Freon gas. Furthermore, when approximately 2 nm of the silicon dioxide film 3 below this is removed, the result is as shown in FIG. 3 (8). Next, as shown in FIG. 3(f), a second gate oxide 7 and a second polycrystalline silicon film 8 are grown and patterned. 1. The shape of the overlapping portion of the second polycrystalline silicon films 6 and 8 is improved as shown in the figure, and the interlayer insulating film 14 is
It is formed uniformly with a thickness of On, m. Next, Figure 3 (q)
As shown in FIG. 1, an N+ diffusion layer 9 and an interlayer insulating film 10 are formed, and an aluminum electrode 11 and a protective film 12 are deposited.

As described above, in the conventional method, protrusions on the surface occur due to the lower dielectric strength of the thin part of the oxide film at the end of the first polycrystalline silicon film and due to the growth of drain of polycrystalline silicon. , the dielectric strength between the two layers of polycrystalline silicon films deteriorates, and etching residues of the second polycrystalline silicon film occur at the overhang portions of the ends of the first polycrystalline silicon film, resulting in defects. However, the present invention has improved this problem.

Effects of the Invention As described above, in the manufacturing method and Li, two-layer polycrystalline silicon structure according to the present invention, the interlayer dielectric strength voltage between the two layers of polycrystalline silicon films is improved, and the shapes of the stems and knobs are improved, and multilayer wiring is realized. 2) A technology that can prevent bridging and disconnection caused by etching residues of the polycrystalline silicon film of j'1 and etching residues of aluminum wiring, etc., and is particularly useful for manufacturing ultra-highly integrated ICs (VLSIs). It is.

[Brief explanation of drawings]

Figure 1 shows an MO with a general two-layer polycrystalline silicon structure.
3. Structure cross-sectional view of an integrated circuit device, FIGS. 2(&) to (d) are manufacturing process diagrams using a conventional method, and FIGS. 3(a) to (q) are MO8 according to a specific embodiment of the present invention. It is a manufacturing process diagram of an integrated circuit device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... First gate oxide film, 4... Silicon tinide film, 5...
First polycrystalline silicon layer, 13...thin polycrystalline silicon film, 14... interlayer insulating film, 8... second polycrystalline silicon layer. Name of agent: Patent attorney Toshio Nakao and 1 other person 41
Figure I 2nd diagram J Figure 2 IC) /41

Claims (3)

[Claims] (1) A step of forming a two-layer insulating film by overlapping a silicon dioxide film and a silicon nitride film on one main surface of a semiconductor substrate, and a step of depositing a first polycrystalline silicon film on this two-layer insulating film. , patterning the first polycrystalline silicon film into a predetermined first electrode shape;
a step of depositing a polycrystalline silicon film thinner than the first polycrystalline silicon film;
A semiconductor device comprising the steps of: oxidizing the surface layer of the polycrystalline silicon film; depositing a second polycrystalline silicon film over the entire surface; and patterning the second polycrystalline silicon film into the shape of a second electrode. Production method. (2) After oxidizing the thin polycrystalline silicon film and the surface layer of the first polycrystalline silicon film, a thin polycrystalline silicon film is formed on the silicon nitride film in the area where the first polycrystalline silicon film pattern is removed. After removing the silicon dioxide film, etching the silicon nitride film in the region in a self-aligned manner using the remaining silicon dioxide film as a mask, and forming a silicon dioxide film by thermal oxidation, a second 2. A method for manufacturing a semiconductor device according to claim 1, wherein a polycrystalline silicon film is deposited. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the thin polycrystalline silicon film and the surface layer of the first polycrystalline silicon film are thermally oxidized in a high-pressure atmosphere.