JPH0220147B2 - - Google Patents
Info
- Publication number
- JPH0220147B2 JPH0220147B2 JP57175069A JP17506982A JPH0220147B2 JP H0220147 B2 JPH0220147 B2 JP H0220147B2 JP 57175069 A JP57175069 A JP 57175069A JP 17506982 A JP17506982 A JP 17506982A JP H0220147 B2 JPH0220147 B2 JP H0220147B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- silicon film
- silicon dioxide
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 84
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 62
- 239000010410 layer Substances 0.000 claims description 32
- 235000012239 silicon dioxide Nutrition 0.000 claims description 31
- 239000000377 silicon dioxide Substances 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 description 19
- 230000015654 memory Effects 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
この発明は２層多結晶シリコン構造を有する
MOS集積回路装置を形成する際に、前記２層の
多結晶シリコンの層間絶縁耐圧の向上、及び第１
の多結晶シリコン層の段差形状を改善して、アル
ミ配線などの断線、ブリツジなどの防止を可能に
した半導体装置の製造法に関する。[Detailed Description of the Invention] Industrial Application Field This invention has a two-layer polycrystalline silicon structure.
When forming a MOS integrated circuit device, it is necessary to improve the interlayer dielectric breakdown voltage of the two layers of polycrystalline silicon, and to
The present invention relates to a method of manufacturing a semiconductor device, which improves the step shape of a polycrystalline silicon layer, thereby making it possible to prevent disconnections and bridging of aluminum wiring, etc.
従来例の構成とその問題点
近時、MOSダイナミツクメモリーの大容量
（高集積）化に伴い、メモリーセルサイズの縮小
化が要望されているが、メモリーセルの容量の増
加、いわゆる高集積化は動作上、メモリーセルサ
イズの縮小に比例しては縮小できない。このため
メモリーセルサイズの縮小と合わせてメモリーセ
ルを構成する容量部分の絶縁膜を薄くする必要が
生じる。従来、絶縁膜として一般に用いられた熱
酸化膜は膜厚が50nm程度までは均一な良質の膜
形成が可能であつたが、膜厚がこれより薄くなる
と、ピンホールなどが発生し易く、膜厚の低下が
著しい。また、多結晶シリコン、高融点金属など
をゲート電極に用いる２層ゲート構造で、第２ゲ
ート酸化膜もゲート長の縮小にともなつて一段と
うすくなる。例えば、２層多結晶シリコンゲート
電極構造では第１と第２の多結晶シリコンで形成
される２層ゲート間の層間絶縁膜は、第２ゲート
電極下の絶縁膜形成としての基板の熱酸化と同時
に、第１多結晶シリコン膜の表面部を酸化するこ
とにより形成していたが、第２ゲート酸化膜が薄
くなると、この工程は採用できなくなる。縮小化
に対応して、メモリーセルの容量部を構成する絶
縁膜は二酸化珪素と、高誘電体であるチツ化珪素
膜の二層構造とし、また多結晶シリコン層間の層
間絶縁膜を少なくとも200〜300nmとするなどの
要望も生ずる。しかし、従来方法では次に示すよ
うに層間絶縁膜を厚く形成することは困難であつ
た。すなわち、従来の２層多結晶シリコン構造を
例に示す。Conventional configurations and their problems Recently, as MOS dynamic memories have become larger in capacity (higher integration), there has been a demand for smaller memory cell sizes. Due to its operation, it cannot be reduced in proportion to the reduction in memory cell size. For this reason, along with the reduction in memory cell size, it is necessary to thin the insulating film in the capacitive portion that constitutes the memory cell. Conventionally, thermal oxide films commonly used as insulating films have been able to form uniform, high-quality films up to a film thickness of about 50 nm, but when the film thickness becomes thinner, pinholes are likely to occur and the film becomes thinner. There is a significant decrease in thickness. Furthermore, in a two-layer gate structure in which polycrystalline silicon, high melting point metal, or the like is used for the gate electrode, the second gate oxide film also becomes thinner as the gate length is reduced. For example, in a two-layer polycrystalline silicon gate electrode structure, the interlayer insulating film between the two-layer gate formed of first and second polycrystalline silicon is formed by thermal oxidation of the substrate to form an insulating film under the second gate electrode. At the same time, it was formed by oxidizing the surface portion of the first polycrystalline silicon film, but if the second gate oxide film becomes thin, this process cannot be used. In response to miniaturization, the insulating film constituting the capacitive part of the memory cell has a two-layer structure of silicon dioxide and a silicon dioxide film, which is a high dielectric constant, and the interlayer insulating film between the polycrystalline silicon layers has a thickness of at least 200 m There are also demands such as 300nm. However, with the conventional method, it has been difficult to form a thick interlayer insulating film as described below. That is, a conventional two-layer polycrystalline silicon structure will be taken as an example.
第１図に理想状態での２層多結晶シリコン構造
の断面図を示す。同図において、１は半導体基
板、２は選択酸化法により形成された二酸化珪素
膜、３，４はメモリーセルの容量部を構成する絶
縁膜であり、本例ではそれぞれ二酸化珪素膜、チ
ツ化珪素膜の２層絶縁膜である。５は第１層多結
晶シリコン膜よりなる第１電極、６は層間絶縁
膜、７は第２ゲート酸化膜、８は第２層多結晶シ
リコン膜よりなる第２電極、９はN+拡散層、１
０は層間絶縁膜、１１はアルミニウム電極、１２
は素子の保護膜である。 FIG. 1 shows a cross-sectional view of a two-layer polycrystalline silicon structure in an ideal state. In the figure, 1 is a semiconductor substrate, 2 is a silicon dioxide film formed by a selective oxidation method, and 3 and 4 are insulating films constituting the capacitor part of the memory cell. This is a two-layer insulating film. 5 is a first electrode made of a first layer polycrystalline silicon film, 6 is an interlayer insulating film, 7 is a second gate oxide film, 8 is a second electrode made of a second layer polycrystalline silicon film, 9 is an N + diffusion layer ,1
0 is an interlayer insulating film, 11 is an aluminum electrode, 12
is a protective film of the element.
次に、この半導体装置の層間絶縁膜の形成工程
について、第２図ａ〜ｄに従つて説明する。まず
第２図ａの如く、半導体基板１に選択酸化法によ
りフイールド酸化膜２を形成し、二酸化珪素膜
３、チツ化珪素膜４、多結晶シリコン膜５を順次
堆積し、さらに、多結晶シリコン膜５に対しては
リンを蒸着し、熱拡散法により、シート抵抗を約
40Ω／□とする。 Next, a process for forming an interlayer insulating film of this semiconductor device will be explained with reference to FIGS. 2a to 2d. First, as shown in FIG. 2a, a field oxide film 2 is formed on a semiconductor substrate 1 by a selective oxidation method, a silicon dioxide film 3, a silicon dioxide film 4, and a polycrystalline silicon film 5 are sequentially deposited. For film 5, phosphorus is vapor-deposited and the sheet resistance is reduced to approx.
40Ω/□.
次に第２図ｂの如く、多結晶シリコン膜５を写
真食刻法により第１電極の形状にパターン形成し
た後、この多結晶シリコン膜５の表面を熱酸化し
て、二酸化珪素膜６を形成する。他の部分はチツ
化珪素膜４によつて覆われているため、酸化膜は
成長しない。多結晶シリコン膜５を酸化すると、
多結晶シリコン膜表面は、均一には酸化されず、
端部Ａ，Ｂが図の如く、多結晶シリコン膜５と、
チツ化珪素膜４との境界部に酸化膜のうすい部分
が生じ、間隙ができる。この現象は多結晶シリコ
ン膜の酸化膜厚を厚くする程、より発生しやすく
なり、大きな間隙が生じる。この間隙は高温で酸
化すると、やや発生しにくくなるが、高温では、
多結晶シリコンのグレインサイズが大きくなり、
かつ表面に突起が発生し、酸化膜欠陥の原因とな
り、第１、第２多結晶シリコン層間の絶縁性能を
著しく低下させるという別の問題がある。さらに
次工程で第２ゲート絶縁膜形成のために、チツ化
珪素膜４、二酸化珪素膜３を除去するとき、この
間隙部分にエツチング液が入り込み、さらにこの
部分の二酸化珪素膜６の厚さはさらに薄くなり、
層間絶縁性がますます低下する。また、このよう
な部分は洗浄効果も悪く、特性劣化の原因とな
る。 Next, as shown in FIG. 2b, a polycrystalline silicon film 5 is patterned into the shape of the first electrode by photolithography, and then the surface of this polycrystalline silicon film 5 is thermally oxidized to form a silicon dioxide film 6. Form. Since the other portions are covered with the silicon dioxide film 4, no oxide film grows. When polycrystalline silicon film 5 is oxidized,
The surface of the polycrystalline silicon film is not oxidized uniformly,
As shown in the figure, the ends A and B are connected to a polycrystalline silicon film 5,
A thin portion of the oxide film is formed at the boundary with the silicon dioxide film 4, creating a gap. This phenomenon occurs more easily as the oxide film thickness of the polycrystalline silicon film becomes thicker, and larger gaps are created. This gap becomes somewhat less likely to occur when oxidized at high temperatures, but at high temperatures,
The grain size of polycrystalline silicon increases,
Another problem is that protrusions occur on the surface, causing defects in the oxide film, and significantly reducing the insulation performance between the first and second polycrystalline silicon layers. Furthermore, when the silicon dioxide film 4 and the silicon dioxide film 3 are removed in the next step to form a second gate insulating film, the etching solution enters this gap, and the thickness of the silicon dioxide film 6 in this part is further reduced. It becomes even thinner,
Interlayer insulation deteriorates further. Further, such a portion has poor cleaning effect and causes deterioration of characteristics.
次に第２図ｃの如く、第２ゲート絶縁膜７を形
成するための熱酸化を行い、ついで第２層多結晶
シリコン膜８を堆積し、第１層多結晶シリコンと
同様、リン蒸着、熱拡散をする。この工程では、
第２図ｂのＡの部分で多結晶シリコン膜５，８間
の層間絶縁耐圧が低下し、シヨートも発生しやす
くなる。さらに第２図ｂのＢの部分で間隙に第２
層多結晶シリコンのエツチング残り８′が発生し
やすく、この部分では第２層多結晶シリコン膜８
のブリツジが起る。 Next, as shown in FIG. 2c, thermal oxidation is performed to form a second gate insulating film 7, and then a second layer polycrystalline silicon film 8 is deposited, and like the first layer polycrystalline silicon, phosphorus evaporation is performed. Performs heat diffusion. In this process,
At the part A in FIG. 2b, the interlayer dielectric strength voltage between the polycrystalline silicon films 5 and 8 is lowered, and shorts are more likely to occur. Furthermore, at part B in Figure 2b, a second
Etching residue 8' of the polycrystalline silicon layer tends to occur, and in this area, the second polycrystalline silicon film 8
A bridge occurs.
次に第２図ｄの如く、N+拡散領域９、層間絶
縁膜１０、アルミニウム電極１１を形成する。 Next, as shown in FIG. 2d, an N + diffusion region 9, an interlayer insulating film 10, and an aluminum electrode 11 are formed.
以上のように従来の２層多結晶シリコン構造を
有するMOS集積回路荘置においては、パターン
の微細化に伴い、層間絶縁膜形成過程での前記の
問題は避けることができない。 As described above, in a conventional MOS integrated circuit device having a two-layer polycrystalline silicon structure, the above-mentioned problems cannot be avoided in the process of forming an interlayer insulating film as the pattern becomes finer.
発明の目的
そこで、本発明は２層の多結晶シリコン間の層
間絶縁膜を均一に形成し、層間絶縁耐圧の向上
と、第１多結晶シリコンの側面の形状の改善を図
ることを可能にする半導体装置の製造方法を提供
するものである。Purpose of the Invention Therefore, the present invention makes it possible to uniformly form an interlayer insulating film between two layers of polycrystalline silicon, improve the interlayer dielectric breakdown voltage, and improve the shape of the side surface of the first polycrystalline silicon. A method for manufacturing a semiconductor device is provided.
発明の構成
本発明は、半導体基板の一主面に二酸化珪素
膜、チツ化珪素膜を重ねて二層絶縁膜を形成する
工程と、この二層絶縁膜上に第１の多結晶シリコ
ン膜を堆積する工程と、前記第１の多結晶シリコ
ン膜を所定の第１電極形状にパターン形成する工
程と、前記第１電極を含む主面側全面に前記第１
の多結晶シリコン膜よりも薄く、しかも燐を含ま
ない多結晶シリコン膜を堆積する工程と、前記薄
い多結晶シリコン膜および前記第１の多結晶シリ
コン膜の表面層を酸化する工程と、全面に第２の
多結晶シリコン膜を堆積し、これを第２電極形状
にパターン形成する工程からなる半導体装置の製
造方法であり、これにより、第１電極と第２電極
との層間に形成され易かつた間隙の発生を抑え、
その要因を除くことができる。Structure of the Invention The present invention includes a step of forming a two-layer insulating film by overlapping a silicon dioxide film and a silicon titanium film on one main surface of a semiconductor substrate, and forming a first polycrystalline silicon film on the two-layer insulating film. a step of patterning the first polycrystalline silicon film into a predetermined first electrode shape;
a step of depositing a polycrystalline silicon film that is thinner than the polycrystalline silicon film and does not contain phosphorus; a step of oxidizing the surface layer of the thin polycrystalline silicon film and the first polycrystalline silicon film; A method for manufacturing a semiconductor device comprising the steps of depositing a second polycrystalline silicon film and patterning it into the shape of a second electrode. suppresses the occurrence of gaps,
That factor can be eliminated.
実施例の説明 以下に、本発明を実施例により詳しくのべる。Description of examples The present invention will be described in detail below using examples.
第３図ａ〜ｇはこの発明の一実施例である半導
体集積回路装置の製造方法を示す製造工程流れ図
で示す。第３図ａにおいては、１はＰ型シリコン
基板、２は選択酸化法により形成されたフイール
ド酸化膜である。次に第３図ｂの如く、ゲート絶
縁膜を構成する二酸化珪素膜３、チツ化珪素膜４
を形成し、さらに、第１多結晶シリコン膜５を
500nm成長し、ついで、これにリン蒸着すること
により、多結晶シリコン膜５のシート抵抗を40
Ω／□とする。次に、この第１多結晶シリコン膜
５をレジストを用いた写真食刻法によりパターン
形成する。多結晶シリコン膜５のみエツチング
し、チツ化珪素膜４は残し、次いで、第３図ｃの
如く、その主面側の全面に薄い多結晶シリコン膜
１３を約10nm堆積する。これを800℃、８Kg／cm2
の高圧でウエツト酸化をし、第３図ｄの如く、層
間絶縁膜１４を300nm成長する。この過程で、薄
い多結晶シリコン膜１３は全て酸化され、第１多
結晶シリコン膜５の存在しないチツ化珪素膜４上
に、二酸化珪素膜１５が約200Å成長する。従来
方法では、第一多結晶シリコンの表面のみを酸化
していたが均一に酸化されず、端部に酸化膜の薄
い部分が生じていたが、表面にリン拡散を施して
いない多結晶シリコン膜１３を堆積することによ
り、酸化膜１４，１５は均一に成長し、端部の異
常が著しく改善される。さらに、多結晶シリコン
膜５のグレイン成長及び突起の発生も、これによ
りかなり減少する効果が見られる。なおこの突起
の発生は多結晶シリコン膜５のリン濃度、酸化温
度などの影響を受ける。常圧での高温酸化より
も、低温高圧酸化が有効である。次に、全面に酸
化膜エツチをすることにより、二酸化珪素膜１５
を除去する。また、その後、二酸化珪素膜１４を
マスクとして、チツ化珪素膜４の露出部分をフレ
オンガスを用いたプラズマエツチングにより除去
する。さらに、この下の二酸化珪素膜３を約
20nmを除去すると、第３図ｅの如くなる。次に、
第３図ｆの如く、第２ゲート酸化７、第２多結晶
シリコン膜８を成長し、パターン形成する。第
１、第２多結晶シリコン膜５，８の重なりあう部
分の形状は図のように改善され、層間絶縁膜１４
が250nmの厚さで均一に形成される。次に第３図
ｇの如く、N+拡散層９、層間絶縁膜１０を形成
し、アルミニウム電極１１、保護膜１２を堆積す
る。 3a to 3g are manufacturing process flowcharts showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. In FIG. 3a, 1 is a P-type silicon substrate, and 2 is a field oxide film formed by a selective oxidation method. Next, as shown in FIG. 3b, a silicon dioxide film 3 and a silicon dioxide film 4 forming the gate insulating film are
, and further, a first polycrystalline silicon film 5 is formed.
By growing the polycrystalline silicon film 5 to a thickness of 500 nm and then depositing phosphorus thereon, the sheet resistance of the polycrystalline silicon film 5 is increased to 40 nm.
Let Ω/□. Next, this first polycrystalline silicon film 5 is patterned by photolithography using a resist. Only the polycrystalline silicon film 5 is etched, leaving the silicon nitride film 4, and then, as shown in FIG. 3c, a thin polycrystalline silicon film 13 of about 10 nm is deposited on the entire main surface side. This is heated to 800℃ and 8Kg/cm 2
Wet oxidation is performed at a high pressure of 300 nm, and an interlayer insulating film 14 is grown to a thickness of 300 nm, as shown in FIG. 3d. In this process, the thin polycrystalline silicon film 13 is completely oxidized, and a silicon dioxide film 15 of about 200 Å is grown on the silicon dioxide film 4 where the first polycrystalline silicon film 5 is not present. In the conventional method, only the surface of the first polycrystalline silicon was oxidized, but it was not oxidized uniformly, resulting in thin oxide film parts at the edges. By depositing oxide film 13, oxide films 14 and 15 grow uniformly, and abnormalities at the edges are significantly improved. Furthermore, the effect of significantly reducing grain growth and protrusion generation in the polycrystalline silicon film 5 can be seen. Note that the occurrence of this protrusion is influenced by the phosphorus concentration of the polycrystalline silicon film 5, the oxidation temperature, etc. Low-temperature, high-pressure oxidation is more effective than high-temperature oxidation at normal pressure. Next, by etching the oxide film over the entire surface, the silicon dioxide film 15 is
remove. Thereafter, using the silicon dioxide film 14 as a mask, the exposed portion of the silicon dioxide film 4 is removed by plasma etching using Freon gas. Furthermore, the silicon dioxide film 3 below this is
If 20 nm is removed, the result will be as shown in Figure 3e. next,
As shown in FIG. 3f, a second gate oxide 7 and a second polycrystalline silicon film 8 are grown and patterned. The shape of the overlapping portion of the first and second polycrystalline silicon films 5 and 8 is improved as shown in the figure, and the interlayer insulating film 14
is uniformly formed with a thickness of 250 nm. Next, as shown in FIG. 3g, an N + diffusion layer 9 and an interlayer insulating film 10 are formed, and an aluminum electrode 11 and a protective film 12 are deposited.
以上のように従来方法では、第１多結晶シリコ
ン膜の端部の酸化膜の薄い部分での絶縁耐圧の低
下、及び多結晶シリコンのグレインの成長により
表面の突起が発生し、２層の多結晶シリコン膜間
の絶縁耐圧が悪くなり、又、第１多結晶シリコン
膜端部のオーバーハングの部分で、第２多結晶シ
リコン膜のエツチング残りが生じて不良原因とな
つていたが、本発明により、このような問題は改
善された。 As described above, in the conventional method, protrusions occur on the surface due to a decrease in dielectric strength in the thin portion of the oxide film at the end of the first polycrystalline silicon film and the growth of grains of polycrystalline silicon, and The dielectric strength between the crystalline silicon films deteriorated, and etching residues of the second polycrystalline silicon film were left at the overhang portions of the ends of the first polycrystalline silicon film, which caused defects. This problem has been resolved.
なお、薄い多結晶シリコン膜１３を均一に酸化
し、突起の少ない二酸化珪素膜１４を形成するこ
とが、２層の多結晶シリコン膜５，８の層間絶縁
耐圧の向上と、半導体装置の信頼性の向上にとつ
て重要である。多結晶シリコン膜１３の酸化によ
り形成された二酸化珪素膜１４の電界破壊強度は
多結晶シリコン膜１３の中に含まれるリンの濃度
に依存しており、ごく微量では影響が少ないが、
リンを含まない多結晶シリコン膜の場合、最も良
質な膜二酸化珪素膜１４が形成される。多結晶シ
リコン膜１３中のリン濃度が増加すると、多結晶
シリコン膜１３を形成する多結晶シリコンの粒径
が拡大するとともに多結晶シリコン膜表面の突起
が激しくなるため、多結晶シリコン膜１３を均一
に酸化して突起の少ない二酸化珪素膜１４を形成
することが困難になる。 Note that uniformly oxidizing the thin polycrystalline silicon film 13 to form a silicon dioxide film 14 with few protrusions improves the interlayer dielectric breakdown voltage of the two-layer polycrystalline silicon films 5 and 8 and improves the reliability of the semiconductor device. It is important for the improvement of The electric field breakdown strength of the silicon dioxide film 14 formed by oxidizing the polycrystalline silicon film 13 depends on the concentration of phosphorus contained in the polycrystalline silicon film 13, and a very small amount has little effect;
In the case of a polycrystalline silicon film that does not contain phosphorus, the highest quality silicon dioxide film 14 is formed. When the phosphorus concentration in the polycrystalline silicon film 13 increases, the grain size of the polycrystalline silicon that forms the polycrystalline silicon film 13 increases, and the protrusions on the surface of the polycrystalline silicon film become more intense, which makes the polycrystalline silicon film 13 uniform. This makes it difficult to form a silicon dioxide film 14 with few protrusions.
発明の効果
以上のように本発明に係る製造方法は、２層多
結晶シリコン構造において、２層の多結晶シリコ
ン膜間の層間絶縁耐圧の向上と、ステツプの形状
改善を図り、多層配線において、第２層の多結晶
シリコン膜のエツチング残り、アルミ配線などの
エツチング残りによるブリツジ、及び断線の防止
が実現でき、とくに、超高集積度IC（VLSI）の
製造に有用な技術である。Effects of the Invention As described above, the manufacturing method according to the present invention aims to improve the interlayer dielectric strength between two layers of polycrystalline silicon films and the shape of the step in a two-layer polycrystalline silicon structure, and to It is possible to prevent bridging and disconnection due to etching residue on the second layer polycrystalline silicon film and aluminum wiring, and is a particularly useful technology for manufacturing ultra-highly integrated ICs (VLSI).
第１図は一般的な２層多結晶シリコン構造を有
するMOS集積回路装置の構造断面図、第２図ａ
〜ｄは従来方法による製造工程図、第３図ａ〜ｇ
は本発明の具体的な一実施例にかかるMOS集積
回路装置の製造工程図である。
１……半導体基板、３……第１ゲート酸化膜、
４……チツ化珪素膜、５……第１多結晶シリコン
層、１３……薄い多結晶シリコン膜、１４……層
間絶縁膜、８……第２多結晶シリコン層。
Figure 1 is a structural cross-sectional view of a MOS integrated circuit device having a general two-layer polycrystalline silicon structure, Figure 2a
- d are manufacturing process diagrams according to the conventional method, Figure 3 a - g
1 is a manufacturing process diagram of a MOS integrated circuit device according to a specific embodiment of the present invention. 1... Semiconductor substrate, 3... First gate oxide film,
4... silicon dioxide film, 5... first polycrystalline silicon layer, 13... thin polycrystalline silicon film, 14... interlayer insulating film, 8... second polycrystalline silicon layer.
Claims (1)
珪素膜の二層からなる絶縁膜を形成する工程と、
この二層絶縁膜上に第１の多結晶シリコン膜を堆
積する工程と、前記第１の多結晶シリコン膜を所
定の第１電極形状にパターン形成する工程と、前
記第１電極を含む全面に前記第１の多結晶シリコ
ン膜よりも薄く、燐を含まない多結晶シリコン膜
を堆積する工程と、前記の薄い多結晶シリコン膜
および第１の多結晶シリコン膜の表面層を酸化す
る工程と、全面に第２の多結晶シリコン膜を堆積
し、この第２の多結晶シリコン膜を第２電極形状
にパターン形成する工程からなる半導体装置の製
造方法。 ２ 薄い多結晶シリコン膜と、第１の多結晶シリ
コン膜の表面層を酸化した後、前記第１の多結晶
シリコン膜パターンの除かれた領域のチツ化珪素
膜上に形成された薄い二酸化珪素膜を除去し、残
存する二酸化珪素膜をマスクとして前記領域のチ
ツ化珪素膜を自己整合的にエツチングする工程
と、熱酸化により二酸化珪素膜を形成する工程を
経た後、第２の多結晶シリコン膜を堆積する特許
請求の範囲第１項に記載の半導体装置の製造方
法。 ３ 薄い多結晶シリコン膜と、第１の多結晶シリ
コン膜の表面層の熱酸化を高圧気圏中で行う特許
請求の範囲第１項に記載の半導体装置の製造方
法。[Claims] 1. A step of forming an insulating film consisting of two layers of a silicon dioxide film and a silicon titanide film on one main surface of a semiconductor substrate;
a step of depositing a first polycrystalline silicon film on the two-layer insulating film; a step of patterning the first polycrystalline silicon film into a predetermined first electrode shape; a step of depositing a polycrystalline silicon film that is thinner than the first polycrystalline silicon film and does not contain phosphorus; a step of oxidizing the surface layer of the thin polycrystalline silicon film and the first polycrystalline silicon film; A method for manufacturing a semiconductor device comprising the steps of depositing a second polycrystalline silicon film over the entire surface and patterning the second polycrystalline silicon film in the shape of a second electrode. 2. After oxidizing the thin polycrystalline silicon film and the surface layer of the first polycrystalline silicon film, a thin silicon dioxide film is formed on the silicon dioxide film in the region from which the first polycrystalline silicon film pattern is removed. After removing the film, etching the silicon dioxide film in the region in a self-aligned manner using the remaining silicon dioxide film as a mask, and forming a silicon dioxide film by thermal oxidation, a second polycrystalline silicon film is etched. A method for manufacturing a semiconductor device according to claim 1, which comprises depositing a film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the thin polycrystalline silicon film and the surface layer of the first polycrystalline silicon film are thermally oxidized in a high-pressure atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17506982A JPS5965452A (en) | 1982-10-05 | 1982-10-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17506982A JPS5965452A (en) | 1982-10-05 | 1982-10-05 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5965452A JPS5965452A (en) | 1984-04-13 |
| JPH0220147B2 true JPH0220147B2 (en) | 1990-05-08 |
Family
ID=15989681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17506982A Granted JPS5965452A (en) | 1982-10-05 | 1982-10-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5965452A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434098A (en) * | 1993-01-04 | 1995-07-18 | Vlsi Techology, Inc. | Double poly process with independently adjustable interpoly dielectric thickness |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5430785A (en) * | 1977-08-12 | 1979-03-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5656641A (en) * | 1979-10-13 | 1981-05-18 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1982
- 1982-10-05 JP JP17506982A patent/JPS5965452A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5430785A (en) * | 1977-08-12 | 1979-03-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5656641A (en) * | 1979-10-13 | 1981-05-18 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5965452A (en) | 1984-04-13 |
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