JPS5963724A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPS5963724A JPS5963724A JP17491482A JP17491482A JPS5963724A JP S5963724 A JPS5963724 A JP S5963724A JP 17491482 A JP17491482 A JP 17491482A JP 17491482 A JP17491482 A JP 17491482A JP S5963724 A JPS5963724 A JP S5963724A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- electrode
- protective film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、表面に酸化膜を備えだシリコンウェハを基板
とする集積回路の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing an integrated circuit using a silicon wafer as a substrate having an oxide film on its surface.
従来例の構成とその問題点
第１図〜第４図に従来例のこの種集積回路の構成とその
製造方法を示す。1 to 4 show the structure of a conventional integrated circuit of this type and its manufacturing method.
まず、シリコンウェハ１を基板として配線と抵抗体を形
成する場合、電気絶縁膜としてその基板表面に酸化シリ
コン膜２を形成し利用する。そして、配線パターン電極
３と抵抗パターン４の保護のため、両パターンに保護膜
５を密着させる。さらに電極を取り出しワイヤボンディ
ングランドを形成するため保護膜５の一部を７オトエソ
チングにより除去する、従来は除去部以外は第２図およ
び第３図に示すようにレジスト膜６にて覆い、保護膜５
がエツチングされないようにするが、レジスト膜６にピ
ンホール７を生じさせないことは製造上困離である、
このレジスト膜６のピンホール７が存在する場合、保護
膜５と酸化シリコン膜２は同材質膜のため表面から下地
シリコンウェハ１まで穴８が貫通し、電気特性の劣化や
信頼性に問題を生じる原因となるものであった。First, when wiring and resistors are formed using a silicon wafer 1 as a substrate, a silicon oxide film 2 is formed and used as an electrical insulating film on the surface of the substrate. Then, in order to protect the wiring pattern electrode 3 and the resistor pattern 4, a protective film 5 is attached to both patterns. Furthermore, in order to take out the electrode and form a wire bonding land, a part of the protective film 5 is removed by etching. Conventionally, the area other than the removed part is covered with a resist film 6 as shown in FIGS. 2 and 3, and the protective film 5 is removed. 5
However, it is difficult in manufacturing to prevent pinholes 7 from forming in the resist film 6. If pinholes 7 exist in the resist film 6, the protective film 5 and the silicon oxide film 2 are the same. Because of the material film, holes 8 penetrate from the surface to the base silicon wafer 1, causing deterioration of electrical characteristics and reliability problems.
発明の目的
本発明は上記の点に鑑みなされたものであり、表面に酸
化膜を有したシリコンウェハを基板とする集積回路の保
護膜の窓あけ方法として、特殊工法を組み合わせること
により、従来と同様の酸化シリコン膜で、しかもピンホ
ールを生じさぜない低不良率、高信頼性の保護膜を作成
する集積回路の製造方法を提供することを目的とする。Purpose of the Invention The present invention has been made in view of the above points, and is a method for opening a protective film of an integrated circuit using a silicon wafer having an oxide film on the surface as a substrate. It is an object of the present invention to provide a method for manufacturing an integrated circuit that uses a similar silicon oxide film to create a protective film that does not cause pinholes, has a low defect rate, and has high reliability.
発明の構成
そこでこの目的を達成するために本発明の集積回路の製
造方法は表面に酸化シリコン膜を形成したシリコンウェ
ハな基板とし、その基板上に配線用電極と抵抗パターン
を形成し、これらの上に保護膜をかふせるとともにその
保護膜と上記電極の間にレジストパターンを形成し、そ
のレジスト除去により上記保護膜の窓あけを行う構成と
したものである〜
この構成により、レジスト膜除去の際に同時にその上に
形成されている保護膜も取り去られ、電極用窓ができる
こととなり、電極用窓の形成の際。Structure of the Invention In order to achieve this object, the integrated circuit manufacturing method of the present invention uses a silicon wafer substrate with a silicon oxide film formed on its surface, forms wiring electrodes and a resistance pattern on the substrate, and processes these by forming wiring electrodes and resistance patterns on the substrate. The structure is such that a protective film is covered over the top, a resist pattern is formed between the protective film and the electrode, and a window is opened in the protective film by removing the resist. At the same time, the protective film formed thereon is also removed, creating an electrode window.
酸化シリコンを溶かすエツチング液を使用ぜす、レジス
トのピンホールの有無は信頼性劣化−や電気特性不良に
無関係にすることができる。By using an etching solution that dissolves silicon oxide, the presence or absence of pinholes in the resist can be made irrelevant to reliability deterioration or poor electrical characteristics.
実施例の説明
以下、本発明の一実施例を図面を参照して説明する。捷
ず、第６図に示すようにシリコンウニ／・９の上に電気
絶縁膜として酸化シリコン膜１０を形成し基板とする。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 6, a silicon oxide film 10 is formed as an electrical insulating film on the silicon urchin 9 to form a substrate.
その基板上に配線用電極１１と抵抗パターン１２を形成
し、ワイヤボンティング電極の窓あけ用として、その電
極１１の部分にレジスト膜１３を密着させる、次の工程
にて上記基板上に形成されたパターン全体に第６図に示
すように酸化シリコン膜を保護膜１４として覆う。A wiring electrode 11 and a resistor pattern 12 are formed on the substrate, and a resist film 13 is closely adhered to the electrode 11 portion to form a window for the wire bonding electrode. The entire pattern is covered with a silicon oxide film as a protective film 14 as shown in FIG.
そして、次の工程にて上記レジスト膜１３除去の際、第
７図に示すように同時にその上に形成されでいる保護膜
１４も取り去られ、電極用窓１５ができる、この場合、
レジスト膜１３のピンホールが存在しても、酸化シリコ
ンのエツチング液を使用し方いてレジストの剥離液を使
用するため、酸化シリコン膜１ｏと保護膜１４を貫通す
る穴はでき々い、そのためレジストのピンホールに起因
する保８φ膜１４．酸化シリコン膜１０の欠陥発生が防
止でき、電気不良率低減、信頼性向上が達成さ＃Ｌる、
発明の効果
以上のように構成された本発明によれば、次の効果を得
ることができる。 □
■ 保護膜を残しだい部分にレジスト膜をのせる必要が
なくなり、レジスト膜のピンホールによる穴あき、下地
シリコンまでの貫通が発生するという事態は生じ々いた
め素子の信頼性低下。When the resist film 13 is removed in the next step, the protective film 14 formed thereon is also removed at the same time as shown in FIG. 7, and an electrode window 15 is formed.
Even if there are pinholes in the resist film 13, since a silicon oxide etching solution is used and a resist stripping solution is used, it is difficult to form a hole that penetrates the silicon oxide film 1o and the protective film 14. 8φ film 14 due to pinholes. It is possible to prevent the occurrence of defects in the silicon oxide film 10, reduce the electrical failure rate, and improve reliability. Effects of the Invention According to the present invention configured as described above, the following effects can be obtained. . □ ■ It is no longer necessary to place a resist film on the area where the protective film is left, and the reliability of the device decreases because pinholes in the resist film and penetration to the underlying silicon are unlikely to occur.
不良発生等の問題がなくなる。Problems such as occurrence of defects are eliminated.
■ 基板材料、電気絶縁膜、保護膜の材料は従来通りの
シリコノウ５エノ・と酸化シリコン膜のままで、ピンホ
ールによる不良や信頼性劣化問題を角了決することがで
きる。■ The materials for the substrate, electrical insulation film, and protective film remain the same as conventional silicone and silicon oxide films, eliminating defects and reliability deterioration caused by pinholes.
■ 付帯効果として、二酸化シリコンと一酸化シリコン
等の混合膜は、化学的にエツチングができず、細かなパ
ターン形成ができなかったが、上記方法により精密な窓
あけが可能である、■ As an additional effect, mixed films of silicon dioxide and silicon monoxide cannot be chemically etched, making it impossible to form fine patterns, but the above method enables precise window openings.
第１図〜第４図は従来の集積回路の製造方法の工程を示
す一部を断面にて見た斜視図、第５図〜第７図は本発明
に係る集積回路の製造方法の工程を示す一部を断面にて
見た斜視図である、９・・・・・・シリコンウェハ）＝
１０・・・・・・電気絶縁用酸化シリコン膜、１１・・
・・・・配線用電極、１２・・・・・・抵抗体パターン
、１３・・・・・・レジスト膜、１４・・・・・・保護
膜（酸化シリコン膜）、１５・・・・・・保護膜の窓。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第
１１４
第４図
第５図
２
第６図
／／ ｆ２1 to 4 are partially sectional perspective views showing steps in a conventional integrated circuit manufacturing method, and FIGS. 5 to 7 show steps in an integrated circuit manufacturing method according to the present invention. It is a perspective view of a part shown in cross section, 9... silicon wafer) =
10...Silicon oxide film for electrical insulation, 11...
... Wiring electrode, 12 ... Resistor pattern, 13 ... Resist film, 14 ... Protective film (silicon oxide film), 15 ...・Protective film window. Name of agent: Patent attorney Toshio Nakao and 1 other person
114 Figure 4 Figure 5 Figure 2 Figure 6 // f2
Claims (1)
し、その上に配線用電極と抵抗体パターンを形成し、こ
れらの上に保護膜をかぶせるとともにその保護膜と上記
電極の間にレジストパターンを形成し、そのレジスト除
去により上記保護膜の窓あけを行うことを特徴とする集
積回路の製造方法。A silicon wafer with a silicon oxide film on the surface is used as a substrate, wiring electrodes and resistor patterns are formed on it, a protective film is placed over these, and a resist pattern is formed between the protective film and the above electrodes. A method for manufacturing an integrated circuit, characterized in that a window is opened in the protective film by removing the resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17491482A JPS5963724A (en) | 1982-10-04 | 1982-10-04 | Manufacture of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17491482A JPS5963724A (en) | 1982-10-04 | 1982-10-04 | Manufacture of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5963724A true JPS5963724A (en) | 1984-04-11 |
Family
ID=15986905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17491482A Pending JPS5963724A (en) | 1982-10-04 | 1982-10-04 | Manufacture of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5963724A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5122369A (en) * | 1974-08-19 | 1976-02-23 | Suwa Seikosha Kk | Handotaisochino seizohoho |
-
1982
- 1982-10-04 JP JP17491482A patent/JPS5963724A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5122369A (en) * | 1974-08-19 | 1976-02-23 | Suwa Seikosha Kk | Handotaisochino seizohoho |
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